DQSPI - Serial Peripheral Interface Master/Slave with single, dual and quad SPI Bus support
Block Diagram
Overview
The DQSPI is a revolutionary quad SPI designed to offer the fastest available operations for any serial SPI memory. It is flexible enough to interface directly with numerous standard product peripherals from several manufacturers. Moreover, IP Core supports all 8, 16, 32 bit processors available on the market. The DQSPI is a fully configurable SPI master/slave device, which allows user to configure polarity and phase of serial clock signal SCK. It lets the microcontroller to communicate with fast serial SPI memories and serial peripheral devices. Moreover, it's capable of interprocessor communications in a multi-master system.
Features
- Operates with 8, 16 and 32 bit CPUs; Full duplex synchronous serial data transfer; DMA support; Support for 32, 16 and 8 bit systems
- Support for various system Bus Standards; Single, Dual and Quad SPI transfer; DDR support (Double Data Rate)
- Optionally available Execute-in-Place; Multimaster system supported; Optional FIFO size extension (128, 256, 512B)
- Up to 8 SPI slaves can be addressed; System error detection; Interrupt generation; Various Bit rates supported
- Bit rate in fast SPI Mode ½ CLK; Four transfer formats; Simple SPU and DMA interface
IP Quality Metrics
| Basic | |
|---|---|
| Year IP was first released | 2012 |
| Latest version of Quartus supported | 15.1 |
| Altera Customer Use | |
| IP has been successfully implemented in production with at least one customer | Y |
| Deliverables | |
Customer deliverables include the following:
|
Y |
| Any additional customer deliverables provided with IP | TBD |
| Parameterization GUI allowing end user to configure IP | Y |
| IP core is enabled for OpenCore Plus Support | Y |
| Source language | Verilog; VHDL |
| Testbench language | Verilog; VHDL |
| Software drivers provided | Y |
| Driver OS support | TBD |
| Implementation | |
| User Interface | AXI; Avalon-MM |
| IP-XACT Metadata included | N |
| Verification | |
| Simulators supported | ModelSim |
| Hardware validated | Y. Altera Board Name DE1, DE2 |
| Industry standard compliance testing performed | N |
| If No, is it planned? | Y |
| Interoperability | |
| IP has undergone interoperability testing | N |
| Interoperability reports available | N |
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