Digital Core Design is a leading Intellectual Property (IP) Core provider and System-on-Chip (SoC) design house. The company was founded in 1999 and thanks to in-depth specialization and innovative approach we have introduced more than 70 different architectures. Among them you can find e.g. World’s Fastest 8051 CPU, World’s Smallest 8051 CPU, silicon proven and royalty-free 32-bit CPU, Automotive LIN, CAN, CAN-FD, CAN-XL controllers
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DI2S is a universal solution that provides an interface between a microprocessor and I2S, left/right justified modes, PCM, and TDMaudio protocol codec. Thanks to the flexible configuration it can work as a receiver, or transmitter in master or slave mode, with configurable channel length or sample size. Additionally, a number of audio blocks can be adjusted according to specific project needs.
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The DESPI is a fully configurable eSPI master/slave device supporting all features described in Enhanced Serial Peripheral Interface Base Specification rev. 1.0. The DESPI master is to be used by the microcontroller to communicate with eSPI peripheral devices. The DESPI slave is to be used as an eSPI peripheral device, e.g. an Embedded Controller attached to the Intel® CPU system.
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D8530 bridge to APB, AHB, and AXI bus, it is a dual-channel USART (Universal Synchronous/Asynchronous Receiver/Transmitter) device, designed for use with 8 and 16-bit microprocessors. It works as a serial-to-parallel, parallel-to-serial converter/controller and can be software-configured to satisfy a wide range of serial communications applications. The device contains a variety of new, sophisticated internal functions, including on-chip baud rate generators. The D8530 handles asynchronous formats, synchronous byte-oriented protocols (such as IBM® Bisync), and synchronous bit-oriented protocols, like HDLC and IBM SDLC. This versatile device supports virtually any serial data transfer application (telecommunication, LAN, etc.). It can also generate and check CRC codes in any synchronous mode and can be programmed to check data integrity in various modes. The D8530 supports modem control in both channels – in applications where these controls are not needed, modem controls can be used for general-purpose I/O. You can configure the IP Core to handle all synchronous formats, regardless of data size, stop bits, or parity requirements. The D8530 is controlled through access to 14 Write registers and 7 Read registers per channel (the number of the registers varies depending on the version). Within each operating mode the D8530 allows protocol variations by checking odd or even parity bits, character insertion or deletion, CRC generation, checking break and abort generation and detection, and many other protocol-dependent features.
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The DDMA is a four-channel Direct Memory Access Controller. Its purpose is to transfer data between memories and peripherals to reduce CPU utilization during data transfers. It can be programmed by the CPU via a 32-bit or 8-bit native interface. The DDMA can perform data transactions of configurable size over 32-bit address space. A single transaction size can be set in a range from 1B to 16MB. To limit the negative impact of different reads and writes timing the DDMA features transfer data buffer. This buffer is a 32-bit FIFO memory with configurable depth.
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The D16750 is a soft Core of a Universal Asynchronous Receiver / Transmitter (UART), functionally identical to the TL16C750. The D16750 allows serial transmission in two modes - UART and FIFO. In the FIFO mode, internal FIFOs are activated allowing up to 512 bytes (plus 3 bits data error per byte in the RCVR FIFO) to be stored, both in receive and transmit directions. Our trustworthy core performs serial-to-parallel conversion on data characters, received from a peripheral device or from a MODEM, and a parallel-to-serial conversion on data characters, received from the CPU. The CPU can read a complete status of the UART at any time, during the functional operation. The reported status information includes the type and condition of the transfer operations performed by the UART, as well as any error conditions (parity, overrun, framing or break interrupt).
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Small is beautiful... The DUART is one of the tiniest UART IP Cores available on the market. It is a soft core of a Universal Asynchronous Receiver/Transmitter (UART). It performs serial-to-parallel conversion on data characters received from a peripheral device or a MODEM, and parallel-to-serial conversion on data characters received from the CPU. The CPU can read the complete status of the UART at any time during the functional operation. Status information reported includes the type and condition of the transfer operations being performed by the UART, as well as any error conditions (overrun, framing). The DUART includes a programmable baud rate generator that is capable of dividing the timing reference clock input by divisors of 1 to (216-1), and producing a 16 clock for driving the internal transmitter logic.
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DI2CSB bridge to APB, AHB, and AXI bus, provides an interface between a passive target device e.g. memory, LCD display, pressure sensors, etc., and the I2C bus. It can work as a slave receiver or transmitter depending on a working mode determined by the master device. A very simple interface, composed of reading, write, and data signals, allows easy connection to target devices. The core does not require any programming and is ready to work after power-up/reset. Read, write, burst read, burst write and repeated start transmissions are automatically recognized by the core. The solution incorporates all features required by the I2C specification
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The I2C is a two-wire, bi-directional serial bus, which provides a simple and efficient method of short distance data transmission between many devices. The DI2CMS core provides an interface between a microprocessor/microcontroller and an I2C bus. It can work as a master or a slave transmitter/receiver - depending on a working mode, determined by the microprocessor/microcontroller. The DI2CMS core incorporates all features required by the latest I2C specification, including clock synchronization, arbitration, multi-master systems and a high-speed transmission mode (the DI2CMS supports all the transmission speed modes). Built-in timer allows operation from a wide range of the clk frequencies. The DI2CMS is technology independent, that's why a VHDL or VERILOG design can be implemented in a variety of process technologies. Furthermore, it can be also completely customized in accordance to the customer's needs.The DI2CMS is delivered with fully automated testbench and complete set of tests
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The specification is served at a basis for the IEEE 802.3 standard which specifies the physical and lower software layers. Since its commercial release, Ethernet has retained a good degree of compatibility. Digital core design focuses on innovation, but remembers about standardization. That's why our DMAC solution is a hardware implementation of media access control protocol defined by the IEEE standard. Thanks to our IP core a functionality in design has never been better before. The DMAC in cooperation with external PHY device enables network functionality in design. It is capable to transmit and receive Ethernet frames to and from the network. Half and full duplex modes are supported, as well 10 and 100 Mbit/s speed. The core is able to work with wide range of processors: 8, 16 and 32 bit data bus, either little or big endian byte order format. The DMAC provides static configuration of PHY IC. Please remember that our design is technology independent, thus can be implemented in vari.
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DHDLC bridge to APB, AHB, and AXI bus, provides versatile support for a widely used HDLC transmission protocol. It manages the bit stuffing process, both address appending and detection. And if it’s not enough, let’s just mention that DCD’s IP Core supports CRC16 and CRC32 computation. Increased system performance and reduced CPU overload are a must-be, thanks to the presence of separate receiver and transmitter FIFO buffers, maskable interrupt, and DMA interface requests. The DHDLC is a fully scalable IP Core, which makes it a perfect solution for both high-end and deeply embedded projects.
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DI2CM-FIFO bridge to APB, AHB, AXI bus, this core provides an interface between a microprocessor/microcontroller and I2C bus. It can work as:a master transmitter ormaster receiver depending on a working mode determined by the microprocessor/microcontroller. The DI2CM-FIFO core incorporates all features required by the latest I2C specification, including clock synchronization, arbitration, multi-master systems, and high-speed transmission mode. The built-in timer allows operation from a wide range of clk frequencies. The DI2CM-FIFO is a technology-independent design that can be implemented in a variety of process technologies.
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DFSPI bridge to APB, AHB, AXI bus, it is a fully configurable SINGLE, DUAL, QUAD, and OCTAL SPI master/slave device, which allows the user to configure polarity and phase of serial clock signal SCK. As an option, the DFSPI controller has built-in support for HyperBusTM specification and xSPI (Expanded Serial Peripheral Interface – JESD251A) specification. The SPI Controller allows easy communication with the most available SPI FLASH memories.A serial clock line (SCK) synchronizes the shifting and sampling of the information on the serial data lines. It is a technology-independent design that can be implemented in a variety of process technologies. The DFSPI system is flexible enough to interface directly with numerous standard product peripherals from several manufacturers. Clock control logic allows a selection of clock polarity and a choice of two fundamentally different clocking protocols to accommodate the most available synchronous serial peripheral devices.The DFSPI can automatically drive selected by SSCR (Slave Select Control Register) slave select outputs (SS3O – SS0O), and address SPI slave device to exchange serially shifted data. It supports two DMA modes: single transfer and multi-transfer. These modes allow DFSPI to interface to higher-performance DMA units, which can interleave their transfers between CPU cycles or execute multiple byte transfers. DFSPI is fully customizable, which means it is delivered in the exact configuration that meets users’ requirements.
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The DSPI is a fully configurable SPI master/slave device, which allows user to configure polarity and phase of serial clock signal SCK. It allows the microcontroller to communicate with serial peripheral devices. It is also capable of interprocessor communications in a multi-master system. A serial clock line (SCK) synchronizes shifting and sampling of the information on the two independent serial data lines. DSPI data are simultaneously transmitted and received. What's the most important, it's a technology independent design that can be implemented in a variety of process technologies. The DSPI system is flexible enough to interface directly with numerous standard product peripherals from several manufacturers. It can be configured as a master or a slave device, with data rates as high as CLK/4.
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The DQSPI is a revolutionary quad SPI designed to offer the fastest available operations for any serial SPI memory. It is flexible enough to interface directly with numerous standard product peripherals from several manufacturers. Moreover, IP Core supports all 8, 16, 32 bit processors available on the market. The DQSPI is a fully configurable SPI master/slave device, which allows user to configure polarity and phase of serial clock signal SCK. It lets the microcontroller to communicate with fast serial SPI memories and serial peripheral devices. Moreover, it's capable of interprocessor communications in a multi-master system.
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The DI2CM core provides an interface between a microprocessor/microcontroller and I2C bus. It can work as: a master transmitter or - master receiver depending on a working mode determined by the microprocessor/microcontroller. The DI2CM core incorporates all features required by the latest I2C specification, including clock synchronization, arbitration, multi-master systems, and high-speed transmission mode. Built-in timer allows operation from a wide range of clk frequencies. The DI2CM is a technology independent design that can be implemented in variety of process technologies.
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DPSMBUS is a fully-featured module based on the I2C protocol, which supports SMBus and PMBus functionalities. It can operate as a DPSMBUSM – Master and DPSMBUSS – Slave. Due to SMBus and PMBus documentation, the module meets requirements, both for SMBSDA and SMBSCK , for acceptable timing intervals. DSPMBUS module supports arbitration and clock synchronization, which is necessary for multi-master systems. The IP Core, as it’s been suggested in the SMBus documentation, has implemented a reaction on a stuck SMBSCK signal in a low state Ttimeoutmin.
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DI2CS bridge to APB, AHB, AXI bus, provides an interface between a microprocessor/microcontroller and I2C bus. It can work as:a slave transmitter orslave receiverdepending on a working mode determined by the master device. The DI2CS core incorporates all features required by the latest I2C specification, including:clock synchronization,arbitration,high-speed transmission mode.The DI2CS supports all transmission speed modes:Standard (up to 100 kb/s)Fast (up to 400 kb/s)Fast Plus (up to 1 Mb/s)High Speed (up to 3,4 Mb/s)DCD’s IP Core is a technology-independent design and can be implemented in various process technologies.
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The D68000-CPU32 soft core is binary-compatible with the industry standard 68000’s CPU32 version of the 32-bit microcontroller. The D68000-CPU32 has a 16-bit data bus and 24-bit address data bus. It is code compatible with the MC68008, MC68010 and CPU32 (version of MC68020). The D68000-CPU32 has an improved instructions set, which allows program execution with higher performance than the standard 68000 core. It contains a built-in DoCD-BDM debugger interface. The D68000-CPU32 is delivered with fully automated test bench and complete set of tests, allowing easy package validation at each stage of SoC design flow.
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DSMART bridge to APB, AHB, and AXI bus, is a fast, versatile, and cost-competitive core intended for smart card reader applications. It provides a communication interface with a smart card based on ISO 7816-3/EMV4.2/4.3 requirements. DCD’s IP Core implements hardware support for both T0 character-oriented protocol and T1 block-oriented protocol. It was designed to combine highly reduced CPU utilization and low area consumption. The DSMART is able to activate and deactivate cards, perform resets, handle ATR reception, and offers many additional features. Configuration options allow you to adjust the DSMART to your particular needs and choose proprietary options, which will be the most suitable for the design. Data transfer to and from the host system can be interrupt-driven or executed through Direct Memory Access (DMA). The automatic convention detection and decoding mechanism ensures the exact result regardless of the used convention. Elementary Time Unit (ETU) – time duration of one bit is decoded from the received ATR interface byte and generated automatically. The card clock divider provides a non-gated clock with a wide range of possible frequencies. A special power down mode was implemented in which the card clock is being held in two possible states, depending on the card parameter. Error signaling and character repetition are automatic for the T0 protocol. The DSMART also incorporates optional CRC/LRC hardware checking and generation mechanism, which gives a convention-independent result. The received CRC/LRC is not stored in the FIFO but can be read in case of CRC/LRC error. Additionally, the optional block length counter provides security of the DMA block transfer and automatic CRC/LRC, subjoining with a manual affixing option. A special block mode handles block transfer automatically. Status and error registers provide necessary information about the FIFO state, errors, and card events. Note that DSMART works with all major CPUs and is 100% compatible with DCD’s MCUs – enabling the same – cryptography.
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CAN FD FULL IP Core is a missing gap between CAN FD and CAN XL. It is called “CPU friendly” because it efficiently relieves it through configurable registers and few additional innovations. DCD’s CAN FD FULL IP Core is a versatile and adaptable solution for incorporating Controller Area Network (CAN) functionality into various systems. This IP module can be implemented independently, as part of an ASIC, or on an FPGA. It adheres to the ISO11898-1:2015 standard, enabling seamless communication in accordance with popular industry protocols. This module provides support for both classical CAN and CAN FD but to establish a physical connection to the CAN bus, external transceiver hardware is required. DCD’s solution utilizes a single or dual-ported Message RAM, which is located outside of the module itself. This storage medium is connected to the CAN FD Full through the generic master interface, facilitating efficient message handling.
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DMESCC – Dual channel Multiprotocol Enhanced Serial Communication Controller, is designed for use with 8- and 16- bit microprocessors. DMESCC handles asynchronous formats, synchronous byte-oriented protocols such as IBM® Bisync, and synchronous bit-oriented protocols such as HDLC and SDLC. The device can generate and check CRC codes in any synchronous mode and can be programmed to check data integrity in various modes. The DMESCC also has facilities for modem control in both channels. The user can configure DMESCC to handle all asynchronous formats regardless of data size, number of stop bits, or parity requirements. Control is done through the number of control and status registers for each channel separately. Within each operating mode, the DMESCC also allows for protocol variations by checking odd or even parity bits, character insertion or deletion, CRC generation, checking break and abort generation and detection, and many other protocol-dependent features. The ultimate functionality of DMESCC denotes its usability: as a data communications device, DMESCC transmits and receives data in a wide variety of data communication protocols.as a microprocessor peripheral, it offers valuable features such as vectored interrupts, polling, and simple handshake capability. The DMESCC provides two independent full-duplex channels, programmable for use in any standard asynchronous or synchronous data communication protocol. In Asynchronous mode transmission and reception can be accomplished independently on each channel with 5 to 8 bits per character, plus optional even or odd parity. The transmitters can supply one, one-and-half, or two stop bits per character and can provide a break output at any time. The receiver break-detection logic interrupts the CPU.
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DMAC-RMII bridge to APB, AHB, AXI bus, our innovative solution is a hardware implementation of media access control protocol defined by the IEEE standard. The DMAC-RMII, in cooperation with an external PHY device, enables network functionality in design. It is able to transmit and receive Ethernet frames to and from the network. Half and full duplex modes are supported, as well as 10 and 100 Mbit/s speed. The Core can work with a wide range of processors: 8, 16 and 32-bit data bus, either little or big endian byte order format. The DMAC-RMII provides a static configuration of PHY IC. Please remember that our design is technology independent and thus can be implemented in a variety of process technologies. This Core strictly conforms to the IEEE 802.3 standard.
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D16950 bridge to APB, AHB, AXI bus, it is a soft core of a Universal Synchronous and Asynchronous Receiver/Transmitter (UART), functionally compatible to the OX16C950. It allows serial transmission in two modes: UART and FIFO. In the FIFO mode, internal FIFOs are activated allowing 128 bytes (plus 3 bits of error data per byte in the RCVR FIFO) to be stored in both receive and transmit modes. Our efficient Core performs serial-to-parallel conversion on data characters received from a peripheral device or MODEM, but also parallel-to-serial conversion on data characters received from the CPU. The processor can read a complete status of the UART at any time during the functional operation. The reported status information includes a type and condition of transfer operations performed by the UART, as well as any error conditions (parity, overrun, framing or break interrupt). The D16950 includes a programmable baud rate generator which is able to divide a timing reference clock input by divisors of 1 to (216-1) and produce a n × clock for driving internal transmitter logic. Provisions are also included to use this n × clock to drive receiver logic. We also equipped our core with complete MODEM-control capability and processor-interrupt system. Interrupts can be programmed in accordance to your requirements, minimizing computing required to handle the communications link. The D16950 core includes all (16450, 16550, 16650 and 16750) features and additional functions. The D16950 has ICR registers which give additional capabilities of UART work configuration. Data transmission may be synchronized by an external clock connected to the RI (for receiver and transmitter) or DSR (only for receiver) pin. The NMR register allows 9-bit mode transmission with or without special character. Writing and reading from/to FIFO may be controlled by trigger level registers. Trigger level registers may be set any value from 1 to 127. In the FIFO mode, there is a selectable autoflow control feature that can reduce software overload significantly and automatically increase system efficiency by controlling serial data flow through the RTS output and CTS input signals. The Core is perfect for applications where the UART core and microcontroller are clocked by the same clock signal and are implemented inside the same ASIC or FPGA chip. Nevertheless, it’s also a proprietary solution for standalone implementation, where several UARTs are required to be implemented inside a single chip and driven by some off-chip devices. Thanks to a universal interface, D16950 core implementation and verification are very simple, just by eliminating a number of clock trees in the complete system. As all our UART Cores, the D16950 includes fully automated test bench with complete set of tests, allowing easy package validation at each stage of SoC design flow. This efficient solution is a technology independent design that can be implemented in variety of process technologies.
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DHDLC bridge to APB, AHB, AXI bus, provides versatile support for a widely used HDLC transmission protocol. It manages the bit stuffing process, both address appending and detection. And if it’s not enough, let’s just mention that DCD’s IP Core supports CRC16 and CRC32 computation. Increased system performance and reduced CPU overload is a must be, thanks to the presence of separate receiver and transmitter FIFO buffers, maskable interrupt and DMA interface request.The optional Frame Status Buffer stores information about frames size and error conditions. Moreover, the size of the receiver and transmitter FIFO buffers is configurable. You can also easily remove unused features before the synthesis process. All that and much more make the DHDLC an ideal solution for very popular higher level protocol implementations like e.g. PPP (Point-to-Point), X.25, V.42, LAB-B, SDLC, ISDN and many others.
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D2692 bridge to APB, AHB, and AXI bus, it is a dual channel UART Core, software compatible with SC26C92, SCC2692, and SCN2681, with added features and deeper FIFOs. It contains: 8 character receiver, 8-character transmit FIFOs, watchdog timer for each receiver, mode register 0, extended baud rate, programmable receiver, and transmitter interrupts. The D26C92 Dual Universal Asynchronous Receiver/Transmitter (DUART) is a communication device that provides two full-duplex asynchronous receiver/transmitter channels in a single package. It interfaces directly with microprocessors and may be used in a polled or interrupt-driven system, plus, it provides a modem and DMA interface. An operating mode and data format of each channel can be programmed independently. Additionally, each receiver and transmitter can select its operating speed as one of 27 fixed baud rates, a 16X clock derived from a programmable counter/timer, or an external 1X or 16X clock. The baud rate generator and counter/timer can operate directly from a crystal or from external clock inputs. The ability to program the operating speed of the receiver and transmitter independently makes the UART particularly attractive for dual-speed channel applications, such as clustered terminal systems.
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DCD believes that even though something may be small or slow, it can still offer maximal efficiency and ultimate reliability. That’s why our DLIN controller with UART half-duplex enhanced functionality supports transmission speeds between 1kb/s and 20kb/s, which allows us to transmit and receive LIN messages compatible to:LIN 1.3,LIN 2.1and the newest LIN 2.2ADLIN bridge to APB, AHB, and AXI bus, it is a softcore of the local interconnect Network (LIN). This interface is a serial communication protocol, primarily designed to be used in automotive applications. Compared to the CAN, The LIN is slower, but thanks to its simplicity, it is much more cost-effective. Our core is ideal for communication in intelligent sensors and actuators, where the bandwidth and versatility of the CAN is not required. The DLIN core provides an interface between a microprocessor/microcontroller and a LIN bus. It can work as a master or slave LIN node, depending on a work mode determined by the microprocessor/microcontroller. DCD’s controller supports transmission speeds between 1 and 20kb/s, which allows it to transmit and receive LIN messages compatible with LIN 1.3., LIN 2.1, and the newest 2.2A specification. The reported information status includes the type and condition of transfer operations performed by the DLIN, as well as a wide range of LIN error conditions (overrun, framing, parity, timeout). Our core includes a programmable timer that allows for detecting timeout and synchronization errors. The DLIN is described at the RTL level, empowering the target use in FPGA and ASIC technologies. The IP core is available in two versions: basic and safety-enhanced. This sophisticated solution’s been developed as ISO26262-10 safety element out of context. It can optionally be improved by necessary safety mechanisms and provide detailed safety documentation: all ISO26262 soft IP SEooC required work products, which include complete Failure Modes Effects and Detection Analysis FMEDA analysis with step-by-step instruction to help to integrate the IP into the customer’s system and to conduct the system-level safety analysis. All the safety-related work products were checked by a third-party, independent audit. The conducted safety analysis depicts, that the safety metrics are fulfilled and both IPs reach the Automotive Safety Integrity Level ASIL-B (Single Point Fault Metric SPFM > 90%, Latent Fault Metric LFM > 60%). DCD-SEMI delivers a complete FMEDA analysis with step-by-step instructions to help to integrate the IP into the customer’s system and to conduct the system-level safety analysis. This ASIL-B ready design may easily be used in Automotive Safety Systems at the ASIL-B level, but DCD-SEMI may optionally deliver higher ASIL level ready IP. For further information and the optional features please contact our support.