D16950 bridge to APB, AHB, AXI bus, it is a soft core of a Universal Synchronous and Asynchronous Receiver/Transmitter (UART), functionally compatible to the OX16C950. It allows serial transmission in two modes: UART and FIFO. In the FIFO mode, internal FIFOs are activated allowing 128 bytes (plus 3 bits of error data per byte in the RCVR FIFO) to be stored in both receive and transmit modes. Our efficient Core performs serial-to-parallel conversion on data characters received from a peripheral device or MODEM, but also parallel-to-serial conversion on data characters received from the CPU. The processor can read a complete status of the UART at any time during the functional operation. The reported status information includes a type and condition of transfer operations performed by the UART, as well as any error conditions (parity, overrun, framing or break interrupt). The D16950 includes a programmable baud rate generator which is able to divide a timing reference clock input by divisors of 1 to (216-1) and produce a n × clock for driving internal transmitter logic. Provisions are also included to use this n × clock to drive receiver logic. We also equipped our core with complete MODEM-control capability and processor-interrupt system. Interrupts can be programmed in accordance to your requirements, minimizing computing required to handle the communications link. The D16950 core includes all (16450, 16550, 16650 and 16750) features and additional functions. The D16950 has ICR registers which give additional capabilities of UART work configuration. Data transmission may be synchronized by an external clock connected to the RI (for receiver and transmitter) or DSR (only for receiver) pin. The NMR register allows 9-bit mode transmission with or without special character. Writing and reading from/to FIFO may be controlled by trigger level registers. Trigger level registers may be set any value from 1 to 127. In the FIFO mode, there is a selectable autoflow control feature that can reduce software overload significantly and automatically increase system efficiency by controlling serial data flow through the RTS output and CTS input signals. The Core is perfect for applications where the UART core and microcontroller are clocked by the same clock signal and are implemented inside the same ASIC or FPGA chip. Nevertheless, it’s also a proprietary solution for standalone implementation, where several UARTs are required to be implemented inside a single chip and driven by some off-chip devices. Thanks to a universal interface, D16950 core implementation and verification are very simple, just by eliminating a number of clock trees in the complete system. As all our UART Cores, the D16950 includes fully automated test bench with complete set of tests, allowing easy package validation at each stage of SoC design flow. This efficient solution is a technology independent design that can be implemented in variety of process technologies.