DHDLC - HDLC/SDLC controller

Block Diagram

Solution Type: IP Core

End Market: Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement

Evaluation Method: OpenCore Plus

Technology: Processors and Peripherals: Peripherals

Arria Series: Intel® Arria® 10, Arria® V

Cyclone Series: Cyclone® IV, Cyclone® V

MAX Series: Intel® MAX® 10, MAX® V

Stratix Series: Stratix® IV, Stratix® V


The DHDLC IP Core provides versatile support for a widely used HDLC transmission protocol. It manages the bit stuffing process, both address appending and detection. And if it’s not enough, let’s just mention that DCD’s IP Core supports CRC16 and CRC32 computation. Increased system performance and reduced CPU overload is a must be, thanks to the presence of separate receiver and transmitter FIFO buffers, maskable interrupt and DMA interface request. The DHDLC is a fully scalable IP Core, which makes it a perfect solution for both hi-end and deeply embedded projects.


  • Two separate receiver and transmitter interfaces; Two separate, configurable FIFO buffers for receiver and transmitter;
  • Bit stuffing and unstuffing; Address recognition for receiver and address insertion for transmitter; Two or one byte address field;
  • CRC-16 and CRC-32 computation and checking; Collision detection; Byte alignment error detection;
  • Programmable number of bits for idle detection; NRZI coding support; Shared flags, shared zeroes support;
  • Pad fill with flags option; Transmitter clock generation; 8-bit, 16-bit, 32-bit CPU interface.

Device Utilization and Performance

Sample results for Cyclone V: LE/ALM: 507/359 | Memory Bits: 256 | Fmax: 183MHz For more results please refer to the datasheet.

Getting Started

For more information about free evaluation license (available for any selected FPGA) or commercial product, please contact us at: aleads@dcd.pl | +48 32 2828266 | www.dcd.pl

IP Quality Metrics

Year IP was first released2013
Latest version of Quartus supported18.0
Altera Customer Use
IP has been successfully implemented in production with at least one customerY

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Any additional customer deliverables provided with IP
Parameterization GUI allowing end user to configure IPY
IP core is enabled for OpenCore Plus SupportY
Source language
Verilog; VHDL
Testbench languageVerilog; VHDL
Software drivers providedY
Driver OS supportTBD
User InterfaceAXI; Avalon-MM
IP-XACT Metadata includedN
Simulators supportedModelSim
Hardware validated Y. Altera Board Name DE1, DE2
Industry standard compliance testing performed
If No, is it planned?Y
IP has undergone interoperability testing
Interoperability reports available  Y

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