D8254 - Programmable Interval Timer
Block Diagram
Overview
The D8254 is a programmable interval timer/counter, binary compatible with the 82C54 industry standard. Since DCD's core value is innovation, this unique IP Core solves one of the most common problems in any micro-computer system: the generation of accurate time delays under software control. The D8254 can be used as: - Real time clock - Even counter - Digital one-shot - Programmable rate generator - Square wave generator - Binary rate multiplier - Complex waveform generator - Complex motor controller - Interrupt on terminal count The D8254 includes fully automated test bench with complete set of tests , which allows an easy package validation at each stage of SoC design flow. Our proprietary core is a technology independent design that can be implemented in a variety of process technologies.
IP Quality Metrics
| Basic | |
|---|---|
| Year IP was first released | 2006 |
| Latest version of Quartus supported | 18.0 |
| Altera Customer Use | |
| IP has been successfully implemented in production with at least one customer | Y |
| Deliverables | |
Customer deliverables include the following:
|
Y |
| Parameterization GUI allowing end user to configure IP | Y |
| IP core is enabled for OpenCore Plus Support | Y |
| Source language | Verilog; VHDL |
| Testbench language | Verilog; VHDL |
| Software drivers provided | Y |
| Driver OS support | TBD |
| Implementation | |
| User Interface | AXI; Avalon-MM |
| IP-XACT Metadata included | N |
| Verification | |
| Simulators supported | ModelSim |
| Hardware validated | Y. Altera Board Name DE1, DE2 |
| Industry standard compliance testing performed | N |
| If No, is it planned? | Y |
| Interoperability | |
| IP has undergone interoperability testing | N |
| Interoperability reports available | Y |
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