D8254 - Programmable Interval Timer

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: OpenCore Plus

Technology: Processors and Peripherals: Peripherals

Arria Series: Arria® V

Cyclone Series: Cyclone® IV, Cyclone® V

MAX Series: MAX® V

Stratix Series: Stratix® IV, Stratix® V


The D8254 is a programmable interval timer/counter, binary compatible with the 82C54 industry standard. Since DCD's core value is innovation, this unique IP Core solves one of the most common problems in any micro-computer system: the generation of accurate time delays under software control. The D8254 can be used as: - Real time clock - Even counter - Digital one-shot - Programmable rate generator - Square wave generator - Binary rate multiplier - Complex waveform generator - Complex motor controller - Interrupt on terminal count The D8254 includes fully automated test bench with complete set of tests , which allows an easy package validation at each stage of SoC design flow. Our proprietary core is a technology independent design that can be implemented in a variety of process technologies.


  • Three independent 16-bit counters; Six programmable Counter modes; Binary or BCD counting
  • Status Read Back Command; Simple interface allows easy connection to microcontrollers
  • Fully synthesizable
  • Static design and no internal tri-states

Device Utilization and Performance

Sample utilization and performance results for Cyclone II are as follows: Speed Grade: -6| Fmax: 166 MHz For more results please refer to the datasheet.

Getting Started

For more information about free evaluation license (available for any selected FPGA) or commercial product, please contact us at: aleads@dcd.pl | +48 32 2828266 | www.dcd.pl

IP Quality Metrics

Year IP was first released2006
Latest version of Quartus supported18.0
Altera Customer Use
IP has been successfully implemented in production with at least one customerY

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Parameterization GUI allowing end user to configure IPY
IP core is enabled for OpenCore Plus SupportY
Source language
Verilog; VHDL
Testbench languageVerilog; VHDL
Software drivers providedY
Driver OS supportTBD
User InterfaceAXI; Avalon-MM
IP-XACT Metadata includedN
Simulators supportedModelSim
Hardware validated Y. Altera Board Name DE1, DE2
Industry standard compliance testing performed
If No, is it planned?Y
IP has undergone interoperability testing
Interoperability reports available  Y

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