NVMe IP core
Block Diagram

Overview
NVMe IP core interfaces Ultra high-speed PCIe SSD without CPU and external memory. The performance of the latest version drastically improves with built-in optimized PCIe bridge. It achieves over 3300MB/s (read) and over 2100MB/s (Write) ultra high-speed transfer.The new NVMe IP core is very low FPGA resource. This is also lead to less power consumption. It is the best solution for applications which require ultra high-speed performance with compact system. For more information go to: http://www.dgway.com/NVMe-IP_A_E.html
Features
- Implement application layer to access NVMe PCIe SSD without CPU and external memory
- Support 6 commands, i.e. IDENTIFY, WRITE, READ, Shutdown, SMART, and Flush
- Direct connect to Avalon-ST Hard IP for PCI Express from Intel by using 128-bit bus interface, Very low resource usage and low power consumption
- Automatic 512/4K sector LBA support
- Reference design with AB16-PCIeXOVR adapter board is available on Intel FPGA boards
IP Quality Metrics
Basic | |
---|---|
Year IP was first released | 2016 |
Latest version of Quartus supported | 16.0 |
Altera Customer Use | |
IP has been successfully implemented in production with at least one customer | Y |
Deliverables | |
Customer deliverables include the following:
|
Y |
Any additional customer deliverables provided with IP | Reference Design |
Parameterization GUI allowing end user to configure IP | N |
IP core is enabled for OpenCore Plus Support | N |
Source language | VHDL |
Testbench language | VHDL |
Software drivers provided | N |
Driver OS support | N/A |
Implementation | |
User Interface | Other: Customized |
IP-XACT Metadata included | N |
Verification | |
Simulators supported | N/A |
Hardware validated | Y. Altera Board Name Arria V GX, Arria 10 GX, Arria 10 SX, Stratix 10 GX |
Industry standard compliance testing performed | N |
If No, is it planned? | N |
Interoperability | |
IP has undergone interoperability testing | Y |
Interoperability reports available | N |
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