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NVMe IP core

Block Diagram

Solution Type: IP Core

End Market: Broadcast, Computer & Storage, Industrial, Medical, Military, Test & Measurement

Evaluation Method: Source Code

Technology: Interface Protocols: PCI Express

Arria Series: Intel® Arria® 10, Arria® V, Intel® Arria® 10 SoC

Cyclone Series: Cyclone® V, Cyclone® V SoC

Segments:

Supported Device Family:

Solution Type:

Overview

NVMe IP core interfaces Ultra high-speed PCIe SSD without CPU and external memory. The performance of the latest version drastically improves with built-in optimized PCIe bridge. It achieves over 3300MB/s (read) and over 2100MB/s (Write) ultra high-speed transfer.The new NVMe IP core is very low FPGA resource. This is also lead to less power consumption. It is the best solution for applications which require ultra high-speed performance with compact system. For more information go to: http://www.dgway.com/NVMe-IP_A_E.html

Features

Implement application layer to access NVMe PCIe SSD without CPU and external memory
Simple user interface by dgIF typeS
Direct connect to Avalon-ST Hard IP for PCI Express from Intel by using 128-bit bus interface
Very low resource usage and low power consumption
Reference design with AB16-PCIeXOVR adapter board available on Intel FPGA boards

Device Utilization and Performance

Read speed:Over 3300MB/sec, Write speed: Over 2100MB/sec. Very low FPGA resource: Less than 1200 ALMs. // Arria10 SX (10AS066N3F40E2SGE2) Fmax= 280 MHz, Logic utilization=1144 ALMs, Block Memory bit=2,162,688

Getting Started

1st Step: Download free evaluation sof file from DesignGateway official website / 2nd Step: Adapter board is provided from DesignGateway / 3rd Step: Evaluate the IP core performance / 4th Step: Purchasing IP core / http://www.dgway.com/NVMe-IP_A_E.html

IP Quality Metrics

Basic
Year IP was first released	2016
Latest version of Quartus supported	16.0
Altera Customer Use
IP has been successfully implemented in production with at least one customer	Y
Deliverables
Customer deliverables include the following: Design file (encrypted source code or post-synthesis netlist) Simulation model for ModelSim Altera edition Timing and/or layout constraints Testbench or design example Documentation with revision control Readme file	Y
Any additional customer deliverables provided with IP	Reference Design
Parameterization GUI allowing end user to configure IP	N
IP core is enabled for OpenCore Plus Support	N
Source language	VHDL
Testbench language	VHDL
Software drivers provided	N
Driver OS support	N/A
Implementation
User Interface	Other: Customized
IP-XACT Metadata included	N
Verification
Simulators supported	ModelSim - Intel® FPGA Edition
Hardware validated	Y. Altera Board Name Arria V GX, Arria 10 GX, Arria 10 SX
Industry standard compliance testing performed	N
If No, is it planned?	N
Interoperability
IP has undergone interoperability testing	Y
Interoperability reports available	N

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