From Creonic

Request Evaluation
Documentation

IEEE 802.11n/ac LDPC Decoder

Overview

Features

Device Utilization

Getting Started

IP Quality Metrics

Block Diagram

Solution Type: IP Core

End Market: Broadcast, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: OpenCore Plus

Technology: DSP: Error Detection and Correction

Arria Series: Intel® Arria® 10, Arria® V, Intel® Arria® 10 SoC, Arria® V SoC

Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC

Stratix Series: Stratix® IV, Stratix® V

Overview

The WiFi family of standards (IEEE 802.11) is used for Wireless Local Area Networks (WLANs). Its first ver- sion from 1997 has been extended by many amandments such as IEEE 802.11n-2009 (now part of IEEE 802.11- 2012). This amendment was developed in particular for high throughputs of 600 Mbit/s on the air interface. The standard uses convolutional codes for forward error cor- rection as minimum requirement. LDPC codes are op- tional but because of their superiority over convolutional codes they are widely used today. The Creonic IEEE 802.11 LDPC decoder is a high per- formance implementation for WLAN and further applica- tions and supports all LDPC codes as defined by the standard.

Features

    Device Utilization and Performance

    support for all LDPC block lengths (648, 1296, and 1944 bits)

    Getting Started

    Please contact the Creonic Sales Team!

    IP Quality Metrics

    Basic
    Year IP was first released2013
    Latest version of Quartus supported15.1
    Altera Customer Use
    IP has been successfully implemented in production with at least one customerY
    Deliverables

    Customer deliverables include the following:

    • Design file (encrypted source code or post-synthesis netlist)
    • Simulation model for ModelSim Altera edition
    • Timing and/or layout constraints
    • Testbench or design example
    • Documentation with revision control
    • Readme file
    		 Y
    Any additional customer deliverables provided with IP
    		no
    Parameterization GUI allowing end user to configure IPN
    IP core is enabled for OpenCore Plus SupportY
    Source language
    		VHDL
    Testbench languageVHDL
    Software drivers providedN
    Driver OS supportn/a
    Implementation
    User InterfaceOther: proprietary
    IP-XACT Metadata includedN
    Verification
    Simulators supportedModelSim, RivieraPRO
    Hardware validated N. Altera Board Name DE1, DE2
    Industry standard compliance testing performed
    		N
    If No, is it planned?Y
    Interoperability
    IP has undergone interoperability testing
    		N
    Interoperability reports available  N

    Design Solutions Network Members provide products and/or services that are sold or licensed by the Member and not Altera or its affiliates. Altera and its affiliates hereby disclaim any express or implied warranty of any kind including warranties of merchantability, noninfringement of intellectual property, or fitness for any particular purpose with respect to any such products and/or services.

    Find more DSN members
    Find more DSN IP
    Find more DSN boards