SHA-256: 256-bit SHA Cryptoprocessor Core
Block Diagram

Overview
The SHA-256 encryption IP core is a fully compliant implementation of the Message Digest Algorithm SHA-256. It computes a 256-bit message digest for messages of up to (2**64 – 1) bits.Developed for easy reuse, the SHA-256 is available optimized for several technologies with competitive utilization and performance characteristics. Support for the AMBA bus interface is available as an option.
IP Quality Metrics
Basic | |
---|---|
Year IP was first released | 2007 |
Latest version of Quartus supported | 15.1 |
Altera Customer Use | |
IP has been successfully implemented in production with at least one customer | N |
Deliverables | |
Customer deliverables include the following:
|
Y |
Any additional customer deliverables provided with IP | Bit Accurate Model |
Parameterization GUI allowing end user to configure IP | N |
IP core is enabled for OpenCore Plus Support | Y |
Source language | Verilog; VHDL |
Testbench language | Verilog; VHDL |
Software drivers provided | N |
Driver OS support | N/A |
Implementation | |
User Interface | Other: generic uP; AMBA |
IP-XACT Metadata included | N |
Verification | |
Simulators supported | ModelSim, Questa, NC-SIM |
Hardware validated | N. Altera Board Name Altera Cyclone V SOC Board |
Industry standard compliance testing performed | N |
If No, is it planned? | N |
Interoperability | |
IP has undergone interoperability testing | N |
Interoperability reports available | N |
Design Solutions Network Members provide products and/or services that are sold or licensed by the Member and not Altera or its affiliates. Altera and its affiliates hereby disclaim any express or implied warranty of any kind including warranties of merchantability, noninfringement of intellectual property, or fitness for any particular purpose with respect to any such products and/or services.