JPEG-E-S: Baseline JPEG Encoder
About this offer
This IP core supports the Baseline Sequential DCT mode of the ISO/IEC 10918-1 standard. It implements an area-efficient, high-performance, hardware JPEG encoder with very low processing latency. The JPEG-E-S Encoder produces compressed JPEG images and the video payload for Motion-JPEG container formats. It accepts images with 8-bit color samples and up to four color components, in all widely-used color subsampling formats. The encoder processes one color sample per clock cycle, enabling it to compress multiple Full-HD channels even in low-cost FPGAs. One of the smallest JPEG encoders available, it synthesizes to about 3,500 ALMs. The core operates without any assistance from the host processors, and uses AXI-stream interfaces for pixel and stream data, and a 32-bit APB slave interface for registers access. FEATURES: Performs Baseline Sequential DCT JPEG encoding of images or video for ASICs or FPGAs, with small silicon area, high performance, and low latency. Standards Support ISO/IEC 10918-1 Standard Baseline Sequential DCT mode Encodes single-frame JPEG images and Motion JPEG payloads 8-bit per color samples Up to four color components; any image size up to 64k x 64k Handles all scan configurations and all JPEG formats APP, COM, and restart markers Programmable Huffman and Quantization tables Rate Control Options Image: Limits the size of each individual frame Video: Regulates bit rate over a number of input frames Interfaces AXI Streaming I/O data interfaces APB Control/Status interface Optional AHB wrapper with DMA capabilities Performance and Size One encoded sample per clock cycle Small silicon footprint (about 70k ASIC gates) Ease of Integration Automatic program-once/encode-many operation Simple, dedicated timestamps interface Included bit-accurate software model generates test vectors, expected results, and core programming values Optional Raster-to-Block Conversion with AXI or standard memory interface to the lines buffer Format Available as a netlist for ASICs or FPGAs
Technical Specifications
- Category:
- Software and IP Cores: FPGA Intellectual Property Cores: DSP: Video and Image Processing
- End Customer Type:
-
Small and Medium sized Business
Other
Enterprise
Resources
Included Intel Technology
Intel® Cyclone® 10 FPGAs
Intel® Arria® 10 FPGAs and SoC FPGAs
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Founded in 1993, CAST continues to thrive as the longest-running — and most experienced — independent IP supplier. Our mission has been to provide proven, low-risk IP cores, under simple and flexible licensing terms, coupled with outstanding support. The years of work we have done to perfect IP reuse, improve IP quality standards, and refine sales and business practices yield a product line and a partner network that offer you a better IP experience, today and in the future. Proven, Low-Risk IP: Our goal is to maximize IP benefits for our customers by delivering high-quality, easy-to-use, cost-effective solutions to real system development challenges. CAST quality standards are high, and all our IP undergoes rigorous verification and testing before it gets to you. We use industry-standard verification methodologies, develop and test prototypes, participate in industry collaboration plugfests, and more to ensure proper functioning and smooth integration. Our practices have been extensively tested and proven, as we have helped thousands of customers ship billions of units in hundreds of application areas. Simple, Flexible Licensing: We help you get to work quickly, with fine-tuned project options and licensing terms that ensure smooth legal sign-off. Most CAST IP is available royalty-free, and is extremely cost-effective. Outstanding Support: CAST IP comes with some of the best customer support in the industry. Our goal is to help make you successful, not just sell you IP, and we have the experience and resources to make that happen.
Jpeg-e-s: Baseline Jpeg Encoder
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