HyperRAM Controller
Block Diagram

Overview
The new HyperRAM memories, based on low-power PSRAM technology, are very welcome addition to the traditional RAM memories portfolio.They provide good bandwidth performance while using a limited amount of pins.The interface, known as « HyperBus », offers a low signal count (Address, Command and Data using only eight DQ pins), Low Power consumption, Hidden Refresh, Automotive Temperature. These memories are optimized for Mobile and Automotive applications. Typical power consumption during burst read is about 60mA.ALSE has then designed a very-low resource usage HyperBus Memory Controller, in order to provide an easy interface to the HyperRAM memories, along with high performance (up to 333 MBytes/s, which is x1.5 times faster than a 16 bits PSRAM running @ 108MHz).
Features
- Up to 333MBytes/s, with only 12 pins used and only 60mA power consumption
- Very low resource usage, enabling IP integration in the smallest FPGA
- Burst Oriented access, for optimized access and bandiwdth
- User Access to HyperRAM registers, to configure memory settings (Output drive strength, Burst wrap, etc ...)
- Sophisticated SDC Timing Constraints, for easy Timing Convergence. Easy integration thanks to QIP file.
IP Quality Metrics
Basic | |
---|---|
Year IP was first released | 2016 |
Latest version of Quartus supported | 17.0 |
Altera Customer Use | |
IP has been successfully implemented in production with at least one customer | Y |
Deliverables | |
Customer deliverables include the following:
|
Y |
Any additional customer deliverables provided with IP | QIP File, hw_tcl for Qsys / Platform Designer integration |
Parameterization GUI allowing end user to configure IP | Y |
IP core is enabled for OpenCore Plus Support | Y |
Source language | Verilog |
Testbench language | Verilog |
Software drivers provided | N |
Driver OS support | No Software needed |
Implementation | |
User Interface | Avalon-MM; Other: AXI can be provided |
IP-XACT Metadata included | N |
Verification | |
Simulators supported | Modelsim Intel Edition |
Hardware validated | Y. Altera Board Name Cyclone 10 LP FPGA Evaluation Kit |
Industry standard compliance testing performed | N |
If No, is it planned? | N |
Interoperability | |
IP has undergone interoperability testing | N |
Interoperability reports available | N |
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