Simulation Page (Settings Dialog Box)

You open this dialog box by clicking EDA Tool Settings in the Settings dialog box, and then clicking Simulation.

Allows you to specify options for generating VHDL Output File (.vho) Definition, Verilog Output File (.vo) Definition and corresponding Standard Delay Format Output File (.sdo) Definition. You can also select options for generating a script file that you can use to generate a Value Change Dump File (.vcd) Definition for use with other EDA simulation tools. If you select a specific EDA simulation tool, the EDA Netlist Writer selects the default settings for that tool. You can change the settings in this dialog box, and you can click Reset to restore settings to the original defaults. If you have defined customized settings previously, you can select Custom in the Tool name list to use those option settings.

Note: If you include an IP core in your design, you may be prompted to add a Quartus Prime Standard Edition IP File (.qip) Definition or a Quartus Prime Standard Edition Simulation IP File (.sip) Definition. Both of these files are created automatically for some IP cores when you generate that IP core.