Simulation Page (Settings Dialog Box)
Parent topic: Simulation Page (Settings Dialog Box)

Run gate-level simulation automatically after compilation

Directs the selected simulation EDA tool to run a gate-level simulation automatically after the Quartus® Prime Standard Edition software compiles the design.

The simulation tool processes the VHDL Output File, Verilog Output File, orStandard Delay Format Output Files that are generated during compilation.

Scripting Information

Keyword:eda_run_tool_automatically

Settings:on | off*

*default
Related information

Scripting Information
Parent topic: Simulation Page (Settings Dialog Box)

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