EDA Netlist Writer settings

The following options modify how and where the EDA Netlist Writer generates output files.

• Time scale— Directs the EDA Netlist Writer to represent timing delays with the specified time units in each Verilog Output File or Standard Delay Format Output Files. The selected value for the Time Scale option may be between 1 picosecond and 1 millisecond.

• Format for output netlist— Allows you to select VHDL or Verilog HDL as the format for the netlist output of the active simulation or timing tool. Select VHDL to generate EDA Netlist Writer VHDL Output Files, and Verilog HDL to generate Verilog Output Files.

• Output directory— Type or browse to the location you want to use as the output directory for the specified EDA simulation tool. The default name contains the type of tool or output format, followed by the tool name. For example, the default value for the ModelSim simulation software is simulation/modelsim.

• Map illegal HDL characters— Turning this option on directs the EDA Netlist Writer to map illegal characters for VHDL or Verilog HDL.

If you selected VHDL in the Format for output netlist list, the EDA Netlist writer maps non-alphanumeric characters, including brackets ([]), parentheses, (()), angle brackets (<>), and braces ({}) to (_a) in VHDL Output Files. This option generates VHDL 1987 compatible names.

If you selected Verilog HDL in the Format for output netlist list, the EDA Netlist writer maps the vertical bar (|), tilde (~), and colon (:) characters in Quartus^® Prime Standard Edition hierarchical node names to the legal Verilog HDL characters z, x, and underscore (_), respectively, in Verilog Output Files. Turning on this option also maps other illegal non-alphanumeric characters, including brackets ([]), parentheses, (()), angle brackets (<>), and braces ({}) to underscore (_).

• Enable glitch filtering— Turning this option on directs the EDA Netlist Writer to perform glitch filtering when generating VHDL Output Files, Verilog Output Files, and the corresponding Standard Delay Format Output Files for use with other EDA simulation tools.

During simulation, a glitch occurs when transitions of a signal occur too quickly to allow the signal to fully propagate over the routing between the source and destination ports. Glitch filtering removes all pulses that are shorter than the glitch interval length, allowing for more accurate reporting of signal transitions during simulation. The glitch filtering enabled by this option only removes glitches that occur over device routing.

You can also use this option to produce more accurate power analysis results when you us a Value Change Dump File generated by an EDA simulation tool while performing power analysis in the Quartus^® Prime Standard Edition PowerPlay Power Analyzer.