About Location Assignments

Location assignments allow you to control placement of all physical resources on the device. Location assignments assign specific logic to specific resources on the device.

The most common type of location assignment is a pin assignment. You must make pin assignments in order for the design to function properly and you should make location assignments for all pins in the design. The main interface for creating pin assignments is in the Pin Planner. Pin assignments are also commonly created with Tcl scripts.

To create a location assignment in a Tcl script, use the set_location_assignment command:

set_location_assignment -to <signal name> <location>

For example,

set_location_assignment -to data_input Pin_A3

Valid locations are pin location names. Some device families also support edge and I/O bank locations. Edge locations are EDGE_BOTTOM, EDGE_LEFT, EDGE_TOP, and EDGE_RIGHT. I/O bank locations include IOBANK_1 up to IOBANK_n, where n is the number of I/O banks in a particular device.

In addition to pin assignments, you can also control the placement of logic elements, DSP blocks, and RAM blocks on the device. You can create new location assignments, or you can view and change existing assignments in the Assignment Editor and the Chip Planner.

LogicLock regions are flexible, reusable floorplan constraints that increase your ability to guide logic placement on the target device. In addition to saving intermediate synthesis results, LogicLock regions support team-oriented, modular design by enabling you to optimize logic blocks individually, then import them and their placement constraints into a larger design.

A LogicLock region is a user-defined rectangular region. When you assign nodes or entities to a LogicLock region, you direct the Fitter to place those nodes or entities inside the region during fitting. You can create LogicLock regions in the LogicLock Regions window, the Project Navigator, the Design Partitions Planner, the Design Partitions window, and the Chip Planner. There are four types of LogicLock regions:

Fixed-size, locked location
Fixed-size, floating location
Auto-size, floating location
Soft regions (allows the Fitter to place the design elements outside region boundaries)

The Fitter determines an optimal size and location for auto-size and floating regions during compilation. If you are satisfied with the size or location, you can back-annotate the size or location for reuse on subsequent compilations.

For more information on LogicLock regions, see About LogicLock Regions.

You can back-annotate the nodes in the design to the locations to which they were assigned during the previous compilation. Back-annotating nodes is useful if you want to manually place certain nodes without affecting other nodes in order to achieve a fit. You should back-annotate nodes only when the design is finalized and no further changes are expected because back-annotation creates strict Compiler restrictions and can cause illegal assignments.

For more information on back-annotation, see About Back-Annotating Assignments.