You can use routing back-annotation to preserve the routing of an entire design, or a single LogicLock region. During routing back-annotation, the Fitter saves the routing constraints in a Routing Constraints File (.rcf). You can back-annotate routing by selecting Pin, cell, routing & device assignments in the Back-Annotate Assignments (default type) dialog box or by turning on Routing in the Back-Annotate Assignments (advanced type) dialog box. Routing back-annotation is available only for supported device(MAX II) families.

When to avoid routing constraints

Routing constraints require that you do not change the design between the time of back-annotation and the implementation of back-annotated assignments. In addition, there are some circumstances under which it is not appropriate or beneficial to use routing constraints; in particular, routing constraints should not be used in the following cases:

• Node locations are changed or non-existent— If you perform routing back-annotation through the graphical user interface, the locations for all nodes are back-annotated to the logic element level by default. In contrast, if you perform routing back-annotation through the Tcl interface (or if location back-annotation is explicitly turned off in the GUI), the Quartus II software does not save the location information.

• The Netlist Optimizations logic option is turned on—the Netlist Optimizations logic option can create changes to the design that are potentially not reproducible. Subsequent compilations might produce slightly different netlists, making routing and location constraints suboptimal or even impossible. You can verify if your design uses the Netlist Optimizations logic option in the Physical Synthesis Optimizations page of the Settings dialog box.
  
  You can use routing back-annotation together with netlist optimizations under the following circumstances:

• 1. If you create a LogicLock region without using netlist optimizations and back-annotate it with the Prevent further netlist optimizations option, you can then use the LogicLock region in a design that uses netlist optimizations. The entities in the LogicLock region are not affected by subsequent optimizations, and their existing routing and placement information is preserved.

  2. If your design uses the Netlist Optimizations logic option, you can still back-annotate routing by creating a Verilog Quartus Mapping File (.vqm) to preserve netlist changes. The safest way to preserve a fit is to back-annotate the netlist, routing, and placement.

• The design is substantially changed— Even minor changes to a back-annotated design or LogicLock region can render routing and placement assignments inefficient or even impossible for the Fitter to achieve. Routing and location back-annotation should be used in the final stages of the design or LogicLock region development.

• The device is changed— Routing and placement assignments are valid only for the device for which they were compiled. If you want to compile your design to target a different device, ensure that you first remove all location assignments and delete the Routing Constraints File from the project.

• The timing requirements are changed— Routing and location back-annotation are designed to preserve placement and fitting information. If your timing requirements change, you should remove the routing constraints.

The Quartus II software creates a root region if you back-annotate a LogicLock region containing nodes that are not members of a top-level assignment. The root region is available only for supported device(Arria II GX, Cyclone series, MAX II, and Stratix series) families. Nodes that are not user-assigned to another region, and nodes that the Fitter moved from a user-assigned region, are placed in the root region. In general, nodes that are determined by the Fitter as unassigned to any region, are placed in the root region. The root region is device-size and locked. You can make assignments to the root region in the LogicLock Regions window, but you cannot delete it or modify its size or location. You cannot see the root region in the Chip Planner, however you can see  its back-annotated node locations.

If you create a LogicLock region without netlist optimizations and back-annotate it with the Prevent further netlist optimization option turned on, you can use the region in a design that uses netlist optimizations. The entities in the region are not affected by subsequent optimizations.