Our 10-Gbps Ethernet Hardware Demonstration reference design provides a quick way to implement your 10-Gbps Ethernet (10GbE)-based design in an Intel FPGA, and observe live network traffic flowing through various sections of a system. This design also helps you to verify your 10GbE-based system operation with a 10GbE media access controller (MAC) function and a standard off-the-shelf 10GbE SFP+ pluggable optical module or SFP+ direct coupled copper cable assembly. The 10GbE MAC is validated by the UNH-IOL.
The reference design is built with our 10GbE MAC and XAUI PHY Intel® FPGA IP function with four 3.125-gigabit (Gb) serial transceivers in an Intel FPGA to implement one 10GbE XAUI port. The XAUI port is converted in a dual XAUI to SFP+ high speed mezzanine card (HSMC) (from Terasic) to 10-Gbps serial Ethernet providing network interface via low cost SFP+ optical pluggable module or SFP+ direct coupled cable assembly.
This reference design demonstrates the operation of the 10GbE MAC Intel FPGA IP function up to the maximum wire-speed performance with low-cost SFP+ interface in many loopback hardware configurations, as shown in Figure 1.
- Showcases one instance of the 10GbE MAC and XAUI PHY Intel FPGA IP function supporting 10GbE operations in XAUI mode and with low-cost SFP+ optical module or copper interface. For more information about the 10GbE MAC and XAUI PHY Intel FPGA IP, refer to the 10-Gbps Ethernet MAC Intel FPGA IP Function User Guide (PDF) and the Transceiver PHY IP Core User Guide (PDF).
- System loopbacks at various points in the datapath that control, test, and monitor the 10GbE operations.
- Loop A: XGMII interface local loopback
- Loop B: FPGA serial physical medium attachment (PMA) interface local loopback
- Loop C: Broadcom BCM8727 XGXS loopback
- Loop D: Broadcom BCM8727 PMA serial loopback
- Loop E: External SFP+ optical cable loopback
- Sequential random burst tests with configurable number of packets, payload-data type, and payload size for each burst. A pseudo-random binary sequence (PRBS) generator generates the payload data type in fixed increments or in a random sequence.
- Packet statistics for a PRBS generator and monitor, MAC transmitter (TX), and receiver (RX).
- Packet classification of different frame lengths transmitted and received by the MAC.
- Measure throughput for the traffic received by the traffic monitor.
- Tcl-based System Console user interface that allows you to dynamically control the test, and configure and monitor any registers in this reference design.
Demonstrated Altera Technology
- Stratix® IV GX FPGA
- 10-Gbps Ethernet MAC Intel FPGA IP function
- XAUI PHY Intel FPGA IP function
- Avalon® system interconnect
Quartus® II software version 11.0 with following features:
- USB-Blaster driver
- Qsys system integration tool
- Windows- or Linux-based system console
- ModelSim* simulator