The Reed Solomon II Intel® FPGA IP core offers a fully parameterizable Reed Solomon encoder and decoder. These encoders and decoders are widely used for error detection and correction in a wide range of digital signal processing (DSP) applications for storage, retrieval, and transmission of data. The Reed Solomon II Intel FPGA IP core is designed to support optical transport network (OTN) applications.
Reed Solomon II Intel® FPGA IP Core
Throughput:
- Supports up to 10 Gbps with multiple core instantiation
- Provides 2.5 Gbps throughput for Intel® Stratix® series FPGAs
- Provides 1.28 Gbps throughput for Intel Cyclone® series FPGAs
- Supports up to 16 interleaved channels
The Reed Solomon Intel FPGA IP core generates a fully parameterizable Reed Solomon function, allowing you to set the following parameters:
- Number of bits per symbol (8)
- Number of symbols per code word (range: 204 to 255 )
- Number of check symbols per code word (range: 2 to 66)
- All valid field polynomials
The Reed Solomon Intel FPGA IP core offers the following other features:
- Intellectual property (IP) functional simulation models for use in Intel FPGA supported VHDL and Verilog HDL simulators
- Easy-to-use IP Toolbench interface:
- Generates parameterized encoder or decoder
- Generates customized test bench and customized Tcl script
- Avalon® Streaming (Avalon-ST) interfaces
- DSP Builder for Intel FPGAs ready
Typical expected performance and utilization figures for this IP core are provided in the Reed-Solomon Compiler II User Guide.
For technical support on this IP core, please visit Intel Premier Support. You may also search for related topics on this function in the Knowledge Center.