LDPC Intel® FPGA IP Core

Low-density parity-check (LDPC) codes are linear error correction codes that allow you to transmit messages over noisy channels.

The LDPC intellectual property (IP) core targets these standards:

  • DOCSIS 3.1
    • Decoder only
    • On-the-fly switching between code
  • WiMedia 1.5
    • Encoder/Decoder
    • Variable code-word length
    • Optional on-the-fly switching between code
    • Support short and long frame
  • DVB-S2
    • Encoder
  • NASA
    • Encoder/Decoder (CCSDS compliant)
    • Optional low resource architecture available
    • MSA or layered MSA decoding
  • MATLAB* bit-accurate models for simulation

 

  • All decoders have:
    • MATLAB models
    • Double-buffered architecture to reduce latency and boost throughput
    • Early stopping criterion
    • Parameters for:
      • Input parallelism
      • Decoding parallelism
      • LLR width
      • Attenuation factor

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