5G Low-density parity-check

Low-density parity-check (LDPC) codes are linear error correction codes that allow you to transmit messages over noisy channels. Intel's 5G Low-Density Parity Check (LDPC) Intel® FPGA intellectual property (IP) core is a high-throughput encoder or decoder that is compliant with 3rd Generation Partnership Project (3GPP) 5G specification. LDPC codes offer better spectral efficiency and support the high throughput for 5G new radio (NR). With the flexibility of Intel® FPGAs, various configurations can be designed and implemented and re-designed to support any changes to base graph, code rate, Z and LR width. 

User Guide IP Evaluation and Purchase Find IP

Features

DOCSIS 3.1
  • Decoder
  • On-the-fly switching between code

 
WiMedia 1.5
  • Encoder/Decoder
  • Variable code-word length
  • Optional on-the-fly switching between code
  • Support short and long frame
DVB-S2
  • Encoder
NASA
  • Encoder/Decoder (CCSDS compliant)
  • Optional low resource architecture available
  • MSA or layered MSA decoding
MATLAB* bit-accurate models for simuation

All decoders have: 

  • MATLAB models
  • Double-buffered architecture to reduce latency and boost throughput
  • Early stopping criterion
  • Parameters for:
    • Input parallelism
    • Decoding parallelism
    • LLR width
    • Attenuation factor

Device Support

 

Arria® II GX/GZ

Arria V

Arria 10

Cyclone® IV/ Cyclone V

Cyclone® 10 GX

MAX 10 

Stratix® IV GT/GX/E

Stratix V

Stratix® 10

 

Documentation

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