CIC Intel® FPGA IP Core

  

 

Figure 1. Three-Stage Decimating CIC Filter Used in DDC

 

 

Figure 2. Three-Stage Interpolating Filter Used in DUC

The CIC Intel® FPGA IP core implements a cascaded integrator-comb (CIC) filter with data ports that are compatible with the Avalon® Streaming (Avalon-ST) interface. CIC filters (also known as Hogenauer filters) are computationally efficient for extracting baseband signals from narrow-band sources using decimation. They also construct narrow-band signals from processed baseband signals using interpolation.

CIC filters use only adders and registers; they require no multipliers to handle large rate changes. Therefore, CIC is a suitable and economical filter architecture for hardware implementation, and is widely used in sample-rate-conversion designs, such as digital down converters (DDC) and digital up converters (DUC).

  • Interpolation and decimation filters with variable rate change factors (2 to 32,000), a configurable number of stages (1 to 12), and two differential delay options (1 or 2).
  • Single clock domain with selectable number of interfaces and a maximum of 1,024 channels.
  • Selectable data storage options with an option to use pipelined integrators.
  • Configurable input data width (1 to 32 bits) and output data width (1 to full resolution data width).
  • Selectable output rounding modes (truncation, convergent rounding, rounding up, or saturation) and Hogenauer pruning support.
  • Optimization for speed by specifying the number of pipeline stages used by each integrator.
  • Compensation filter coefficients generation.

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