SDMMC Module Address Map

Registers in the SD/MMC module

Base Address: 0xFF704000

SDMMC Module

Register Offset Width Access Reset Value Description
ctrl 0x0 32 RW 0x0 Control Register
pwren 0x4 32 RW 0x0 Power Enable Register
clkdiv 0x8 32 RW 0x0 Clock Divider Register
clksrc 0xC 32 RW 0x0 SD Clock Source Register
clkena 0x10 32 RW 0x0 Clock Enable Register
tmout 0x14 32 RW 0xFFFFFF40 Timeout Register
ctype 0x18 32 RW 0x0 Card Type Register
blksiz 0x1C 32 RW 0x200 Block Size Register
bytcnt 0x20 32 RW 0x200 Byte Count Register
intmask 0x24 32 RW 0x0 Interrupt Mask Register
cmdarg 0x28 32 RW 0x0 Command Argument Register
cmd 0x2C 32 RW 0x20000000 Command Register
resp0 0x30 32 RO 0x0 Response Register 0
resp1 0x34 32 RO 0x0 Response Register 1
resp2 0x38 32 RO 0x0 Response Register 2
resp3 0x3C 32 RO 0x0 Response Register 3
mintsts 0x40 32 RO 0x0 Masked Interrupt Status Register
rintsts 0x44 32 RW 0x0 Raw Interrupt Status Register
status 0x48 32 RO 0x106 Status Register
fifoth 0x4C 32 RW 0x3FF0000 FIFO Threshold Watermark Register
cdetect 0x50 32 RO 0x1 Card Detect Register
wrtprt 0x54 32 RO 0x1 Write Protect Register
tcbcnt 0x5C 32 RO 0x0 Transferred CIU Card Byte Count Register
tbbcnt 0x60 32 RO 0x0 Transferred Host to BIU-FIFO Byte Count Register
debnce 0x64 32 RW 0xFFFFFF Debounce Count Register
usrid 0x68 32 RW 0x7967797 User ID Register
verid 0x6C 32 RO 0x5342240A Version ID Register
hcon 0x70 32 RO 0xC43081 Hardware Configuration Register
uhs_reg 0x74 32 RW 0x0 UHS-1 Register
rst_n 0x78 32 RW 0x1 Hardware Reset Register
bmod 0x80 32 RW 0x0 Bus Mode Register
pldmnd 0x84 32 WO 0x0 Poll Demand Register
dbaddr 0x88 32 RW 0x0 Descriptor List Base Address Register
idsts 0x8C 32 RW 0x0 Internal DMAC Status Register
idinten 0x90 32 RW 0x0 Internal DMAC Interrupt Enable Register
dscaddr 0x94 32 RO 0x0 Current Host Descriptor Address Register
bufaddr 0x98 32 RO 0x0 Current Buffer Descriptor Address Register
cardthrctl 0x100 32 RW 0x0 Card Threshold Control Register
back_end_power_r 0x104 32 RW 0x0 Back End Power Register
data 0x200 32 RW 0x0 Data FIFO Access