intmask

Allows Masking of Various Interrupts
Module Instance Base Address Register Address
sdmmc 0xFF704000 0xFF704024

Offset: 0x24

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

sdio_int_mask

RW 0x0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ebe

RW 0x0

acd

RW 0x0

sbe

RW 0x0

hle

RW 0x0

frun

RW 0x0

hto

RW 0x0

drt

RW 0x0

rto

RW 0x0

dcrc

RW 0x0

rcrc

RW 0x0

rxdr

RW 0x0

txdr

RW 0x0

dto

RW 0x0

cmd

RW 0x0

re

RW 0x0

cd

RW 0x0

intmask Fields

Bit Name Description Access Reset
16 sdio_int_mask

In current application, MMC-Ver3.3 only Bit 16 of this field is used. Bits 17 to 31 are unused and return 0

Value Description
0x0 SDIO Mask Interrupt Disabled
0x1 SDIO Interrupt Enabled
RW 0x0
15 ebe

Bits used to mask unwanted interrupts. Value of 0 masks interrupts, value of 1 enables interrupt.

Value Description
0x0 End-bit error Mask
0x1 End-bit error No Mask
RW 0x0
14 acd

Bits used to mask unwanted interrupts. Value of 0 masks interrupts, value of 1 enables interrupt.

Value Description
0x0 Auto command done Mask
0x1 Auto command done No Mask
RW 0x0
13 sbe

Bits used to mask unwanted interrupts. Value of 0 masks interrupts, value of 1 enables interrupt.

Value Description
0x0 Start-bit error Mask
0x1 Start-bit error No Mask
RW 0x0
12 hle

Bits used to mask unwanted interrupts. Value of 0 masks interrupts, value of 1 enables interrupt.

Value Description
0x0 Hardware locked write error Mask
0x1 Hardware locked write error No Mask
RW 0x0
11 frun

Bits used to mask unwanted interrupts. Value of 0 masks interrupts, value of 1 enables interrupt.

Value Description
0x0 FIFO underrun/overrun error Mask
0x1 FIFO underrun/overrun error No Mask
RW 0x0
10 hto

Bits used to mask unwanted interrupts. Value of 0 masks interrupts, value of 1 enables interrupt.

Value Description
0x0 Data starvation by host timeout Mask
0x1 Data starvation by host timeout No Mask
RW 0x0
9 drt

Bits used to mask unwanted interrupts. Value of 0 masks interrupts, value of 1 enables interrupt.

Value Description
0x0 Data read timeout Mask
0x1 Data read timeout No Mask
RW 0x0
8 rto

Bits used to mask unwanted interrupts. Value of 0 masks interrupts, value of 1 enables interrupt.

Value Description
0x0 Response timeout Mask
0x1 Response timeout No Mask
RW 0x0
7 dcrc

Bits used to mask unwanted interrupts. Value of 0 masks interrupts, value of 1 enables interrupt.

Value Description
0x0 Data CRC error Mask
0x1 Data CRC error No Mask
RW 0x0
6 rcrc

Bits used to mask unwanted interrupts. Value of 0 masks interrupts, value of 1 enables interrupt.

Value Description
0x0 Response CRC error Mask
0x1 Response CRC error No Mask
RW 0x0
5 rxdr

Bits used to mask unwanted interrupts. Value of 0 masks interrupts, value of 1 enables interrupt.

Value Description
0x0 Receive FIFO data request Mask
0x1 Receive FIFO data request No Mask
RW 0x0
4 txdr

Bits used to mask unwanted interrupts. Value of 0 masks interrupts, value of 1 enables interrupt.

Value Description
0x0 Transmit FIFO data request Mask
0x1 Transmit FIFO data request No Mask
RW 0x0
3 dto

Bits used to mask unwanted interrupts. Value of 0 masks interrupts, value of 1 enables interrupt.

Value Description
0x0 Data transfer over Mask
0x1 Data transfer over No Mask
RW 0x0
2 cmd

Bits used to mask unwanted interrupts. Value of 0 masks interrupts, value of 1 enables interrupt.

Value Description
0x0 Command Done Mask
0x1 Command Done No Mask
RW 0x0
1 re

Bits used to mask unwanted interrupts. Value of 0 masks interrupts, value of 1 enables interrupt.

Value Description
0x0 Response error Mask
0x1 Response error No Mask
RW 0x0
0 cd

Bits used to mask unwanted interrupts. Value of 0 masks interrupts, value of 1 enables interrupt.

Value Description
0x0 Card Detected Mask
0x1 Card Detect No Mask
RW 0x0