ctrl
| Module Instance | Base Address | Register Address |
|---|---|---|
| sdmmc | 0xFF704000 | 0xFF704000 |
Offset: 0x0
Access: RW
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Reserved |
use_internal_dmac RW 0x0 |
Reserved |
|||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved |
ceata_device_interrupt_status RW 0x0 |
send_auto_stop_ccsd RW 0x0 |
send_ccsd RW 0x0 |
abort_read_data RW 0x0 |
send_irq_response RW 0x0 |
read_wait RW 0x0 |
Reserved |
int_enable RW 0x0 |
Reserved |
dma_reset RW 0x0 |
fifo_reset RW 0x0 |
controller_reset RW 0x0 |
|||
ctrl Fields
| Bit | Name | Description | Access | Reset | ||||||
|---|---|---|---|---|---|---|---|---|---|---|
| 25 | use_internal_dmac | Enable and Disable Internal DMA transfers.
|
RW | 0x0 | ||||||
| 11 | ceata_device_interrupt_status | Software should appropriately write to this bit after power-on reset or any other reset to CE-ATA device. After reset, usually CE-ATA device interrupt is disabled (nIEN = 1). If the host enables CE-ATA device interrupt, then software should set this bit.
|
RW | 0x0 | ||||||
| 10 | send_auto_stop_ccsd | Always set send_auto_stop_ccsd and send_ccsd bits together; send_auto_stop_ccsd should not be set independent of send_ccsd. When set, SD/MMC automatically sends internally generated STOP command (CMD12) to CE-ATA device. After sending internally-generated STOP command, Auto Command Done (ACD) bit in RINTSTS is set and generates interrupt to host if Auto CommandDone interrupt is not masked. After sending the CCSD, SD/MMC automatically clears send_auto_stop_ccsd bit.
|
RW | 0x0 | ||||||
| 9 | send_ccsd | When set, SD/MMC sends CCSD to CE-ATA device. Software sets this bit only if current command is expecting CCS (that is, RW_BLK) and interrupts are enabled in CE-ATA device. Once the CCSD pattern is sent to device, SD/MMC automatically clears send_ccsd bit. It also sets Command Done (CD) bit in RINTSTS register and generates interrupt to host if Command Done interrupt is not masked. NOTE: Once send_ccsd bit is set, it takes two card clock cycles to drive the CCSD on the CMD line. Due to this, during the boundary conditions it may happen that CCSD is sent to the CE-ATA device, even if the device signalled CCS.
|
RW | 0x0 | ||||||
| 8 | abort_read_data | After suspend command is issued during read-transfer, software polls card to find when suspend happened. Once suspend occurs software sets bit to reset data state-machine, which is waiting for next block of data. Bit automatically clears once data statemachine resets to idle. Used in SDIO card suspend sequence.
|
RW | 0x0 | ||||||
| 7 | send_irq_response | Bit automatically clears once response is sent. To wait for MMC card interrupts, host issues CMD40, and SD/MMC waits for interrupt response from MMC card(s). In meantime, if host wants SD/MMC to exit waiting for interrupt state, it can set this bit, at which time SD/MMC command state-machine sends CMD40 response on bus and returns to idle state.
|
RW | 0x0 | ||||||
| 6 | read_wait | For sending read-wait to SDIO cards.
|
RW | 0x0 | ||||||
| 4 | int_enable | This bit enables and disable interrupts if one or more unmasked interrupts are set.
|
RW | 0x0 | ||||||
| 2 | dma_reset | This bit resets the DMA interface control logic
|
RW | 0x0 | ||||||
| 1 | fifo_reset | This bit resets the FIFO. This bit is auto-cleared after completion of reset operation.
|
RW | 0x0 | ||||||
| 0 | controller_reset | This bit resets the controller. This bit is auto-cleared after two l4_mp_clk and two sdmmc_clk clock cycles. This resets: - BIU/CIU interface - CIU and state machines - abort_read_data, send_irq_response, and read_wait bits of control register -start_cmd bit of command register Does not affect any registers, DMA interface, FIFO or host interrupts.
|
RW | 0x0 |