hcon

Hardware configurations registers. Register can be used to develop configuration-independent software drivers.
Module Instance Base Address Register Address
sdmmc 0xFF704000 0xFF704070

Offset: 0x70

Access: RO

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

aro

RO 0x0

ncd

RO 0x0

scfp

RO 0x1

ihr

RO 0x1

rios

RO 0x0

dmadatawidth

RO 0x1

dmaintf

RO 0x0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

haddrwidth

RO 0xC

hdatawidth

RO 0x1

hbus

RO 0x0

nc

RO 0x0

ct

RO 0x1

hcon Fields

Bit Name Description Access Reset
26 aro

Area optimized

Value Description
0x0 Not Optimized For Area
RO 0x0
25:24 ncd

Number of clock dividers less one

Value Description
0x0 One Clock Divider
RO 0x0
23 scfp

Clock False Path

Value Description
0x1 Clock False Path Set
RO 0x1
22 ihr

Implement hold register

Value Description
0x1 Implements Hold Register
RO 0x1
21 rios

FIFO RAM location

Value Description
0x0 FIFO RAM Outside IP Core
RO 0x0
20:18 dmadatawidth

Encodes bit width of external DMA controller interface. Doesn't apply to the SD/MMC because it has no external DMA controller interface.

Value Description
0x1 32-bits wide
RO 0x1
17:16 dmaintf

DMA interface type

Value Description
0x0 No External DMA Controller Interface (SD/MMC has its own internal DMA Controller
RO 0x0
15:10 haddrwidth

Slave bus address width less one

Value Description
0xc Width 13 Bits
RO 0xC
9:7 hdatawidth

Slave bus data width

Value Description
0x1 Width 32 Bits
RO 0x1
6 hbus

Slave bus type.

Value Description
0x0 APB Bus
RO 0x0
5:1 nc

Maximum number of cards less one

Value Description
0x0 1 Card
RO 0x0
0 ct

Supported card types

Value Description
0x1 Card Type SD/MMC
RO 0x1