DMAC1_Common Address Map

DW_axi_dmac common register address block


Module Instance	Base Address	End Address
`i_dma__dmac1_ahb_slv__10dc0000__Common_Registers_Address_Block__SEG_L4_AHB_dmac1_s_0x0_0x10000`	`0x10DC0000`	`0x10DC0067`


Register	Offset	Width	Access	Reset Value	Description
`DMAC_IDREG`	`0x0`	`64`	`RO`	`0x0000000000000000`	DW_axi_dmac Component ID Register
`DMAC_COMPVERREG`	`0x8`	`64`	`RO`	`0x0000000000000000`	DW_axi_dmac Component Version Register
`DMAC_CFGREG`	`0x10`	`64`	`RW`	`0x0000000000000000`	DW_axi_dmac Global Configuration Register
`DMAC_CHENREG`	`0x18`	`64`	`RW`	`0x0000000000000000`	DW_axi_dmac Channel Enable Register
`DMAC_INTSTATUSREG`	`0x30`	`64`	`RO`	`0x0000000000000000`	DW_axi_dmac Combined Interrupt Status Register
`DMAC_COMMONREG_INTCLEARREG`	`0x38`	`64`	`WO`	`0x0000000000000000`	DW_axi_dmac Common Register Space Interrupt Clear Register
`DMAC_COMMONREG_INTSTATUS_ENABLEREG`	`0x40`	`64`	`RW`	`0x0000000000000000`	DW_axi_dmac Common Register Space Interrupt Enable Register
`DMAC_COMMONREG_INTSIGNAL_ENABLEREG`	`0x48`	`64`	`RW`	`0x0000000000000000`	DW_axi_dmac Common Register Space Interrupt Signal Enable Register
`DMAC_COMMONREG_INTSTATUSREG`	`0x50`	`64`	`RO`	`0x0000000000000000`	DW_axi_dmac Common Register Space Interrupt Status Register
`DMAC_RESETREG`	`0x58`	`64`	`RW`	`0x0000000000000000`	DW_axi_dmac Software Reset Register
`DMAC_LOWPOWER_CFGREG`	`0x60`	`64`	`RW`	`0x0000000000000000`	DW_axi_dmac Low Power Configuration Register