DMAC_IDREG

         DMAC ID Register contains a 32-bit value that is hardwired and read back by a read to the DW_axi_dmac ID Register.


Module Instance	Base Address	Register Address
`i_dma__dmac1_ahb_slv__10dc0000__Common_Registers_Address_Block__SEG_L4_AHB_dmac1_s_0x0_0x10000`	`0x10DC0000`	`0x10DC0000`

Size: 64

Offset: 0x

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
`RSVD_DMAC_IDREG` `RO 0x0`
47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
`RSVD_DMAC_IDREG` `RO 0x0`
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`DMAC_ID` `RO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`DMAC_ID` `RO 0x0`

DMAC_IDREG Fields


Bit	Name	Description	Access	Reset
63:32	`RSVD_DMAC_IDREG`	DMAC_IDREG Reserved bits - Read Only	`RO`	`0x0`
31:0	`DMAC_ID`	DMAC ID Number.	`RO`	`0x0`