DMAC_COMMONREG_INTCLEARREG 

         Writing 1 to specific field clears the corresponding field in DMAC Common register Interrupt Status Register (DMAC_CommonReg_IntStatusReg).
Module Instance Base Address Register Address
i_dma__dmac1_ahb_slv__10dc0000__Common_Registers_Address_Block__SEG_L4_AHB_dmac1_s_0x0_0x10000 0x10DC0000 0x10DC0038

Size: 64

Offset: 0x38

Access: WO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48

RSVD_DMAC_COMMONREG_INTCLEARREG_63to21

WO 0x0

47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

RSVD_DMAC_COMMONREG_INTCLEARREG_63to21

WO 0x0

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RSVD_DMAC_COMMONREG_INTCLEARREG_63to21

WO 0x0

Clear_MXIF2_BCH_EccPROT_UnCorrERR_IntStat

WO 0x0

Clear_MXIF2_BCH_EccPROT_CorrERR_IntStat

WO 0x0

Clear_MXIF2_RCH1_EccPROT_UnCorrERR_IntStat

WO 0x0

Clear_MXIF2_RCH1_EccPROT_CorrERR_IntStat

WO 0x0

Clear_MXIF2_RCH0_EccPROT_UnCorrERR_IntStat

WO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Clear_MXIF2_RCH0_EccPROT_CorrERR_IntStat

WO 0x0

Clear_MXIF1_BCH_EccPROT_UnCorrERR_IntStat

WO 0x0

Clear_MXIF1_BCH_EccPROT_CorrERR_IntStat

WO 0x0

Clear_MXIF1_RCH1_EccPROT_UnCorrERR_IntStat

WO 0x0

Clear_MXIF1_RCH1_EccPROT_CorrERR_IntStat

WO 0x0

Clear_MXIF1_RCH0_EccPROT_UnCorrERR_IntStat

WO 0x0

Clear_MXIF1_RCH0_EccPROT_CorrERR_IntStat

WO 0x0

Clear_SLVIF_UndefinedReg_DEC_ERR_IntStat

WO 0x0

Clear_SLVIF_CommonReg_WRPARITY_ERR_IntStat

WO 0x0

RSVD_DMAC_COMMONREG_INTCLEARREG_6to4

WO 0x0

Clear_SLVIF_CommonReg_WrOnHold_ERR_IntStat

WO 0x0

Clear_SLVIF_CommonReg_RD2WO_ERR_IntStat

WO 0x0

Clear_SLVIF_CommonReg_WR2RO_ERR_IntStat

WO 0x0

Clear_SLVIF_CommonReg_DEC_ERR_IntStat

WO 0x0

DMAC_COMMONREG_INTCLEARREG Fields

Bit Name Description Access Reset
63:21 RSVD_DMAC_COMMONREG_INTCLEARREG_63to21 
DMAC Common Register Interrupt Clear Register (bits 63to21) Reserved bits - Read Only
 WO 0x0
20 Clear_MXIF2_BCH_EccPROT_UnCorrERR_IntStat 
AXI Master Interface 2 Write Response Channel ECC Protection related Uncorrectable Error Interrupt Clear bit.
This bit is used to clear the corresponding channel interrupt status bit (MXIF2_BCH_EccPROT_UnCorrERR_IntStat in DMAC_CommonReg_IntStatusReg).
Value Description
0x0 Inactive signal. No action taken.
0x1 Clear the MXIF2_BCH_EccPROT_UnCorrERR_IntStat interrupt in the interrupt register DMAC_CommonReg_IntStatusReg
WO 0x0
19 Clear_MXIF2_BCH_EccPROT_CorrERR_IntStat 
AXI Master Interface 2 Write Response Channel ECC Protection related Correctable Error Interrupt Clear bit.
This bit is used to clear the corresponding channel interrupt status bit (MXIF2_BCH_EccPROT_CorrERR_IntStat in DMAC_CommonReg_IntStatusReg).
Value Description
0x0 Inactive signal. No action taken.
0x1 Clear the MXIF2_BCH_EccPROT_CorrERR_IntStat interrupt in the interrupt register DMAC_CommonReg_IntStatusReg
WO 0x0
18 Clear_MXIF2_RCH1_EccPROT_UnCorrERR_IntStat 
AXI Master Interface 2 Read Channel (Other Control signals) ECC Protection related Uncorrectable Error Interrupt Clear bit.
This bit is used to clear the corresponding channel interrupt status bit (MXIF2_RCH1_EccPROT_UnCorrERR_IntStat in DMAC_CommonReg_IntStatusReg).
Value Description
0x0 Inactive signal. No action taken.
0x1 Clear the MXIF2_RCH1_EccPROT_UnCorrERR_IntStat interrupt in the interrupt register DMAC_CommonReg_IntStatusReg
WO 0x0
17 Clear_MXIF2_RCH1_EccPROT_CorrERR_IntStat 
AXI Master Interface 2 Read Channel (Other Control signals) ECC Protection related Correctable Error Interrupt Clear bit.
This bit is used to clear the corresponding channel interrupt status bit (MXIF2_RCH1_EccPROT_CorrERR_IntStat in DMAC_CommonReg_IntStatusReg).
Value Description
0x0 Inactive signal. No action taken.
0x1 Clear the MXIF2_RCH1_EccPROT_CorrERR_IntStat interrupt in the interrupt register DMAC_CommonReg_IntStatusReg
WO 0x0
16 Clear_MXIF2_RCH0_EccPROT_UnCorrERR_IntStat 
AXI Master Interface 2 Read Channel (Data) ECC Protection related Uncorrectable Error Interrupt Clear bit.
This bit is used to clear the corresponding channel interrupt status bit (MXIF2_RCH0_EccPROT_UnCorrERR_IntStat in DMAC_CommonReg_IntStatusReg).
Value Description
0x0 Inactive signal. No action taken.
0x1 Clear the MXIF2_RCH0_EccPROT_UnCorrERR_IntStat interrupt in the interrupt register DMAC_CommonReg_IntStatusReg
WO 0x0
15 Clear_MXIF2_RCH0_EccPROT_CorrERR_IntStat 
AXI Master Interface 2 Read Channel (Data) ECC Protection related Correctable Error Interrupt Clear bit.
This bit is used to clear the corresponding channel interrupt status bit (MXIF2_RCH0_EccPROT_CorrERR_IntStat in DMAC_CommonReg_IntStatusReg).
Value Description
0x0 Inactive signal. No action taken.
0x1 Clear the MXIF2_RCH0_EccPROT_CorrERR_IntStat interrupt in the interrupt register DMAC_CommonReg_IntStatusReg
WO 0x0
14 Clear_MXIF1_BCH_EccPROT_UnCorrERR_IntStat 
AXI Master Interface 1 Write Response Channel ECC Protection related Uncorrectable Error Interrupt Clear bit.
This bit is used to clear the corresponding channel interrupt status bit (MXIF1_BCH_EccPROT_UnCorrERR_IntStat in DMAC_CommonReg_IntStatusReg).
Value Description
0x0 Inactive signal. No action taken.
0x1 Clear the MXIF1_BCH_EccPROT_UnCorrERR_IntStat interrupt in the interrupt register DMAC_CommonReg_IntStatusReg
WO 0x0
13 Clear_MXIF1_BCH_EccPROT_CorrERR_IntStat 
AXI Master Interface 1 Write Response Channel ECC Protection related Correctable Error Interrupt Clear bit.
This bit is used to clear the corresponding channel interrupt status bit (MXIF1_BCH_EccPROT_CorrERR_IntStat in DMAC_CommonReg_IntStatusReg).
Value Description
0x0 Inactive signal. No action taken.
0x1 Clear the MXIF1_BCH_EccPROT_CorrERR_IntStat interrupt in the interrupt register DMAC_CommonReg_IntStatusReg
WO 0x0
12 Clear_MXIF1_RCH1_EccPROT_UnCorrERR_IntStat 
AXI Master Interface 1 Read Channel (Other Control signals) ECC Protection related Uncorrectable Error Interrupt Clear bit.
This bit is used to clear the corresponding channel interrupt status bit (MXIF1_RCH1_EccPROT_UnCorrERR_IntStat in DMAC_CommonReg_IntStatusReg).
Value Description
0x0 Inactive signal. No action taken.
0x1 Clear the MXIF1_RCH1_EccPROT_UnCorrERR_IntStat interrupt in the interrupt register DMAC_CommonReg_IntStatusReg
WO 0x0
11 Clear_MXIF1_RCH1_EccPROT_CorrERR_IntStat 
AXI Master Interface 1 Read Channel (Other Control signals) ECC Protection related Correctable Error Interrupt Clear bit.
This bit is used to clear the corresponding channel interrupt status bit (MXIF1_RCH1_EccPROT_CorrERR_IntStat in DMAC_CommonReg_IntStatusReg).
Value Description
0x0 Inactive signal. No action taken.
0x1 Clear the MXIF1_RCH1_EccPROT_CorrERR_IntStat interrupt in the interrupt register DMAC_CommonReg_IntStatusReg
WO 0x0
10 Clear_MXIF1_RCH0_EccPROT_UnCorrERR_IntStat 
AXI Master Interface 1 Read Channel (Data) ECC Protection related Uncorrectable Error Interrupt Clear bit.
This bit is used to clear the corresponding channel interrupt status bit (MXIF1_RCH0_EccPROT_UnCorrERR_IntStat in DMAC_CommonReg_IntStatusReg).
Value Description
0x0 Inactive signal. No action taken.
0x1 Clear the MXIF1_RCH0_EccPROT_UnCorrERR_IntStat interrupt in the interrupt register DMAC_CommonReg_IntStatusReg
WO 0x0
9 Clear_MXIF1_RCH0_EccPROT_CorrERR_IntStat 
AXI Master Interface 1 Read Channel (Data) ECC Protection related Correctable Error Interrupt Clear bit.
This bit is used to clear the corresponding channel interrupt status bit (MXIF1_RCH0_EccPROT_CorrERR_IntStat in DMAC_CommonReg_IntStatusReg).
Value Description
0x0 Inactive signal. No action taken.
0x1 Clear the MXIF1_RCH0_EccPROT_CorrERR_IntStat interrupt in the interrupt register DMAC_CommonReg_IntStatusReg
WO 0x0
8 Clear_SLVIF_UndefinedReg_DEC_ERR_IntStat 
Slave Interface Undefined register Decode Error Interrupt clear Bit.
This bit is used to clear the corresponding channel interrupt status bit(SLVIF_UndefinedReg_DEC_ERR_IntStat in DMAC_CommonReg_IntStatusReg.
Value Description
0x0 Inactive signal. No action taken.
0x1 Clear the SLVIF_UndefinedReg_DEC_ERR interrupt in the interrupt register DMAC_CommonReg_IntStatusReg
WO 0x0
7 Clear_SLVIF_CommonReg_WRPARITY_ERR_IntStat 
Slave Interface Common Register Write Parity Error Interrupt clear Bit.
This bit is used to clear the corresponding channel interrupt status bit(SLVIF_CommonReg_WRPARITY_ERR_IntStat in DMAC_CommonReg_IntStatusReg.
Value Description
0x0 Inactive signal. No action taken.
0x1 Clear the SLVIF_CommonReg_WRPARITY_ERR interrupt in the interrupt register DMAC_CommonReg_IntStatusReg
WO 0x0
6:4 RSVD_DMAC_COMMONREG_INTCLEARREG_6to4 
DMAC Common Register Interrupt Clear Register (bits 6to4) Reserved bits - Read Only
 WO 0x0
3 Clear_SLVIF_CommonReg_WrOnHold_ERR_IntStat 
Slave Interface Common Register Write On Hold Error Interrupt clear Bit.
This bit is used to clear  the corresponding channel interrupt status bit(SLVIF_CommonReg_WrOnHold_ERR_IntStat in DMAC_CommonReg_IntStatusReg.
Value Description
0x0 Inactive signal. No action taken.
0x1 Clear the SLVIF_CommonReg_WrOnHold_ERR interrupt in the interrupt register DMAC_CommonReg_IntStatusReg
WO 0x0
2 Clear_SLVIF_CommonReg_RD2WO_ERR_IntStat 
Slave Interface Common Register Read to Write only Error Interrupt clear Bit.
This bit is used to clear  the corresponding channel interrupt status bit(SLVIF_CommonReg_RD2WO_ERR_IntStat in DMAC_CommonReg_IntStatusReg.
Value Description
0x0 Inactive signal. No action taken.
0x1 Clear the SLVIF_CommonReg_RD2WO_ERR interrupt in the interrupt register DMAC_CommonReg_IntStatusReg
WO 0x0
1 Clear_SLVIF_CommonReg_WR2RO_ERR_IntStat 
Slave Interface Common Register Write to Read only Error Interrupt clear Bit.
This bit is used to clear the corresponding channel interrupt status bit(SLVIF_CommonReg_WR2RO_ERR_IntStat in DMAC_CommonReg_IntStatusReg.
Value Description
0x0 Inactive signal. No action taken.
0x1 Clear the SLVIF_CommonReg_WR2RO_ERR interrupt in the interrupt register DMAC_CommonReg_IntStatusReg
WO 0x0
0 Clear_SLVIF_CommonReg_DEC_ERR_IntStat 
Slave Interface Common Register Decode Error Interrupt clear Bit.
This bit is used to clear the corresponding channel interrupt status bit (SLVIF_CommonReg_DEC_ERR_IntStat in DMAC_CommonReg_IntStatusReg.
Value Description
0x0 Inactive signal. No action taken.
0x1 Clear the SLVIF_CommonReg_DEC_ERR interrupt in the interrupt register DMAC_CommonReg_IntStatusReg
WO 0x0