DMAC_CHENREG

         This is DW_axi_dmac Channel Enable Register. If software wants to set up a new channel, it can read this register to find out which channels are currently inactive and then enable an inactive channel with the required priority.
All bits of this register are cleared to 0 when the DW_axi_dmac Global Enable bit (DMAC_CfgReg.DMAC_EN) is 0. When DMAC_CfgReg.DMAC_EN is 0, a write to the DMAC_ChEnReg register is ignored and a read always reads back 0.
The channel enable bit, DMAC_ChEnReg.CH_EN, is written only if the corresponding channel write enable bit, DMAC_ChEnReg.CH_EN_WE, is asserted on the same slave interface write transfer. For example, writing hex XXXX01X1 writes a 1 into DMAC_ChEnReg [0], while DMAC_ChEnReg [7:1] remains unchanged. Writing hex XXXX00XX leaves DMAC_ChEnReg [7:0] unchanged.
The channel suspend bit, DMAC_ChEnReg.CH_SUSP, is written only if the corresponding channel write enable bit, DMAC_ChEnReg.CH_SUSP_WE, is asserted on the same slave interface write transfer. For example, writing hex 01X1XXXX writes a 1 into DMAC_ChEnReg [16], while DMAC_ChEnReg [23:17] remains unchanged. Writing hex 00XXXXXX leaves DMAC_ChEnReg [23:16] unchanged. The channel abort bit, DMAC_ChEnReg.CH_ABORT, is written only if the corresponding channel write enable bit, DMAC_ChEnReg.CH_ABORT_WE, is asserted on the same slave interface write transfer.


Module Instance	Base Address	Register Address
`i_dma__dmac1_ahb_slv__10dc0000__Common_Registers_Address_Block__SEG_L4_AHB_dmac1_s_0x0_0x10000`	`0x10DC0000`	`0x10DC0018`

Size: 64

Offset: 0x18

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
`RSVD_DMAC_CHENREG` `RO 0x0`
47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
`CH8_ABORT_WE` `WO 0x0`	`CH7_ABORT_WE` `WO 0x0`	`CH6_ABORT_WE` `WO 0x0`	`CH5_ABORT_WE` `WO 0x0`	`CH4_ABORT_WE` `WO 0x0`	`CH3_ABORT_WE` `WO 0x0`	`CH2_ABORT_WE` `WO 0x0`	`CH1_ABORT_WE` `WO 0x0`	`CH8_ABORT` `RW 0x0`	`CH7_ABORT` `RW 0x0`	`CH6_ABORT` `RW 0x0`	`CH5_ABORT` `RW 0x0`	`CH4_ABORT` `RW 0x0`	`CH3_ABORT` `RW 0x0`	`CH2_ABORT` `RW 0x0`	`CH1_ABORT` `RW 0x0`
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`CH8_SUSP_WE` `WO 0x0`	`CH7_SUSP_WE` `WO 0x0`	`CH6_SUSP_WE` `WO 0x0`	`CH5_SUSP_WE` `WO 0x0`	`CH4_SUSP_WE` `WO 0x0`	`CH3_SUSP_WE` `WO 0x0`	`CH2_SUSP_WE` `WO 0x0`	`CH1_SUSP_WE` `WO 0x0`	`CH8_SUSP` `RW 0x0`	`CH7_SUSP` `RW 0x0`	`CH6_SUSP` `RW 0x0`	`CH5_SUSP` `RW 0x0`	`CH4_SUSP` `RW 0x0`	`CH3_SUSP` `RW 0x0`	`CH2_SUSP` `RW 0x0`	`CH1_SUSP` `RW 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`CH8_EN_WE` `WO 0x0`	`CH7_EN_WE` `WO 0x0`	`CH6_EN_WE` `WO 0x0`	`CH5_EN_WE` `WO 0x0`	`CH4_EN_WE` `WO 0x0`	`CH3_EN_WE` `WO 0x0`	`CH2_EN_WE` `WO 0x0`	`CH1_EN_WE` `WO 0x0`	`CH8_EN` `RW 0x0`	`CH7_EN` `RW 0x0`	`CH6_EN` `RW 0x0`	`CH5_EN` `RW 0x0`	`CH4_EN` `RW 0x0`	`CH3_EN` `RW 0x0`	`CH2_EN` `RW 0x0`	`CH1_EN` `RW 0x0`

DMAC_CHENREG Fields

Bit Name Description Access Reset

63:48

RSVD_DMAC_CHENREG

DMAC_CHENREG Reserved bits - Read Only

RO

0x0

CH8_ABORT_WE

This bit is used to write enable the Channel-8 Abort bit.
The read back value of this register bit is always 0.

Value	Description
0x0	Disable Write to CH8_ABORT bit
0x1	Enable Write to CH8_ABORT bit

WO

0x0

CH7_ABORT_WE

This bit is used to write enable the Channel-7 Abort bit.
The read back value of this register bit is always 0.

Value	Description
0x0	Disable Write to CH7_ABORT bit
0x1	Enable Write to CH7_ABORT bit

WO

0x0

CH6_ABORT_WE

This bit is used to write enable the Channel-6 Abort bit.
The read back value of this register bit is always 0.

Value	Description
0x0	Disable Write to CH6_ABORT bit
0x1	Enable Write to CH6_ABORT bit

WO

0x0

CH5_ABORT_WE

This bit is used to write enable the Channel-5 Abort bit.
The read back value of this register bit is always 0.

Value	Description
0x0	Disable Write to CH5_ABORT bit
0x1	Enable Write to CH5_ABORT bit

WO

0x0

CH4_ABORT_WE

This bit is used to write enable the Channel-4 Abort bit.
The read back value of this register bit is always 0.

Value	Description
0x0	Disable Write to CH4_ABORT bit
0x1	Enable Write to CH4_ABORT bit

WO

0x0

CH3_ABORT_WE

This bit is used to write enable the Channel-3 Abort bit.
The read back value of this register bit is always 0.

Value	Description
0x0	Disable Write to CH3_ABORT bit
0x1	Enable Write to CH3_ABORT bit

WO

0x0

CH2_ABORT_WE

This bit is used to write enable the Channel-2 Abort bit.
The read back value of this register bit is always 0.

Value	Description
0x0	Disable Write to CH2_ABORT bit
0x1	Enable Write to CH2_ABORT bit

WO

0x0

CH1_ABORT_WE

This bit is used to write enable the Channel-1 Abort bit.
The read back value of this register bit is always 0.

Value	Description
0x0	Disable Write to CH1_ABORT bit
0x1	Enable Write to CH1_ABORT bit

WO

0x0

CH8_ABORT

Channel-8 Abort Request.
Software sets this bit to 1 to request channel abort. If this bit is set to 1, DW_axi_dmac disables the channel
immediately. Aborting the channel might result in AXI Protocol violation as DW_axi_dmac does not make sure that all AXI transfers initiated on the master interface are completed.Aborting the channel is not recommended and should be used only in situations where a particular channel hangs due to no response from the corresponding AXI slave interface and software wants to disable the channel without resetting the entire DW_axi_dmac. It is recommended to try channel disabling first and then only opt for channel aborting.
 - 0: No Channel Abort Request. 
 - 1: Request for Channel Abort.
DW_axi_dmac clears this bit to 0 once the channel is aborted (when it sets CH8_Status.CH_ABORTED bit to 1).

Value	Description
0x0	No Request for Channel-8 Abort
0x1	Request for Channel-8 Abort

RW

0x0

CH7_ABORT

Channel-7 Abort Request.
Software sets this bit to 1 to request channel abort. If this bit is set to 1, DW_axi_dmac disables the channel
immediately. Aborting the channel might result in AXI Protocol violation as DW_axi_dmac does not make sure that all AXI transfers initiated on the master interface are completed.Aborting the channel is not recommended and should be used only in situations where a particular channel hangs due to no response from the corresponding AXI slave interface and software wants to disable the channel without resetting the entire DW_axi_dmac. It is recommended to try channel disabling first and then only opt for channel aborting.
 - 0: No Channel Abort Request. 
 - 1: Request for Channel Abort.
DW_axi_dmac clears this bit to 0 once the channel is aborted (when it sets CH7_Status.CH_ABORTED bit to 1).

Value	Description
0x0	No Request for Channel-7 Abort
0x1	Request for Channel-7 Abort

RW

0x0

CH6_ABORT

Channel-6 Abort Request.
Software sets this bit to 1 to request channel abort. If this bit is set to 1, DW_axi_dmac disables the channel
immediately. Aborting the channel might result in AXI Protocol violation as DW_axi_dmac does not make sure that all AXI transfers initiated on the master interface are completed.Aborting the channel is not recommended and should be used only in situations where a particular channel hangs due to no response from the corresponding AXI slave interface and software wants to disable the channel without resetting the entire DW_axi_dmac. It is recommended to try channel disabling first and then only opt for channel aborting.
 - 0: No Channel Abort Request. 
 - 1: Request for Channel Abort.
DW_axi_dmac clears this bit to 0 once the channel is aborted (when it sets CH6_Status.CH_ABORTED bit to 1).

Value	Description
0x0	No Request for Channel-6 Abort
0x1	Request for Channel-6 Abort

RW

0x0

CH5_ABORT

Channel-5 Abort Request.
Software sets this bit to 1 to request channel abort. If this bit is set to 1, DW_axi_dmac disables the channel
immediately. Aborting the channel might result in AXI Protocol violation as DW_axi_dmac does not make sure that all AXI transfers initiated on the master interface are completed.Aborting the channel is not recommended and should be used only in situations where a particular channel hangs due to no response from the corresponding AXI slave interface and software wants to disable the channel without resetting the entire DW_axi_dmac. It is recommended to try channel disabling first and then only opt for channel aborting.
 - 0: No Channel Abort Request. 
 - 1: Request for Channel Abort.
DW_axi_dmac clears this bit to 0 once the channel is aborted (when it sets CH5_Status.CH_ABORTED bit to 1).

Value	Description
0x0	No Request for Channel-5 Abort
0x1	Request for Channel-5 Abort

RW

0x0

CH4_ABORT

Channel-4 Abort Request.
Software sets this bit to 1 to request channel abort. If this bit is set to 1, DW_axi_dmac disables the channel
immediately. Aborting the channel might result in AXI Protocol violation as DW_axi_dmac does not make sure that all AXI transfers initiated on the master interface are completed.Aborting the channel is not recommended and should be used only in situations where a particular channel hangs due to no response from the corresponding AXI slave interface and software wants to disable the channel without resetting the entire DW_axi_dmac. It is recommended to try channel disabling first and then only opt for channel aborting.
 - 0: No Channel Abort Request. 
 - 1: Request for Channel Abort.
DW_axi_dmac clears this bit to 0 once the channel is aborted (when it sets CH4_Status.CH_ABORTED bit to 1).

Value	Description
0x0	No Request for Channel-4 Abort
0x1	Request for Channel-4 Abort

RW

0x0

CH3_ABORT

Channel-3 Abort Request.
Software sets this bit to 1 to request channel abort. If this bit is set to 1, DW_axi_dmac disables the channel
immediately. Aborting the channel might result in AXI Protocol violation as DW_axi_dmac does not make sure that all AXI transfers initiated on the master interface are completed.Aborting the channel is not recommended and should be used only in situations where a particular channel hangs due to no response from the corresponding AXI slave interface and software wants to disable the channel without resetting the entire DW_axi_dmac. It is recommended to try channel disabling first and then only opt for channel aborting.
 - 0: No Channel Abort Request. 
 - 1: Request for Channel Abort.
DW_axi_dmac clears this bit to 0 once the channel is aborted (when it sets CH3_Status.CH_ABORTED bit to 1).

Value	Description
0x0	No Request for Channel-3 Abort
0x1	Request for Channel-3 Abort

RW

0x0

CH2_ABORT

Channel-2 Abort Request.
Software sets this bit to 1 to request channel abort. If this bit is set to 1, DW_axi_dmac disables the channel
immediately. Aborting the channel might result in AXI Protocol violation as DW_axi_dmac does not make sure that all AXI transfers initiated on the master interface are completed.Aborting the channel is not recommended and should be used only in situations where a particular channel hangs due to no response from the corresponding AXI slave interface and software wants to disable the channel without resetting the entire DW_axi_dmac. It is recommended to try channel disabling first and then only opt for channel aborting.
 - 0: No Channel Abort Request. 
 - 1: Request for Channel Abort.
DW_axi_dmac clears this bit to 0 once the channel is aborted (when it sets CH2_Status.CH_ABORTED bit to 1).

Value	Description
0x0	No Request for Channel-2 Abort
0x1	Request for Channel-2 Abort

RW

0x0

CH1_ABORT

Channel-1 Abort Request.
Software sets this bit to 1 to request channel abort. If this bit is set to 1, DW_axi_dmac disables the channel
immediately. Aborting the channel might result in AXI Protocol violation as DW_axi_dmac does not make sure that all AXI transfers initiated on the master interface are completed.Aborting the channel is not recommended and should be used only in situations where a particular channel hangs due to no response from the corresponding AXI slave interface and software wants to disable the channel without resetting the entire DW_axi_dmac. It is recommended to try channel disabling first and then only opt for channel aborting.
 - 0: No Channel Abort Request. 
 - 1: Request for Channel Abort.
DW_axi_dmac clears this bit to 0 once the channel is aborted (when it sets CH1_Status.CH_ABORTED bit to 1).

Value	Description
0x0	No Request for Channel-1 Abort
0x1	Request for Channel-1 Abort

RW

0x0

CH8_SUSP_WE

This bit is used as a write enable to the Channel-8 Suspend bit. The read back value of this register bit is always 0.

Value	Description
0x0	Disable Write to CH8_SUSP bit
0x1	Enable Write to respective CH8_SUSP bit

WO

0x0

CH7_SUSP_WE

This bit is used as a write enable to the Channel-7 Suspend bit. The read back value of this register bit is always 0.

Value	Description
0x0	Disable Write to CH7_SUSP bit
0x1	Enable Write to respective CH7_SUSP bit

WO

0x0

CH6_SUSP_WE

This bit is used as a write enable to the Channel-6 Suspend bit. The read back value of this register bit is always 0.

Value	Description
0x0	Disable Write to CH6_SUSP bit
0x1	Enable Write to respective CH6_SUSP bit

WO

0x0

CH5_SUSP_WE

This bit is used as a write enable to the Channel-5 Suspend bit. The read back value of this register bit is always 0.

Value	Description
0x0	Disable Write to CH5_SUSP bit
0x1	Enable Write to respective CH5_SUSP bit

WO

0x0

CH4_SUSP_WE

This bit is used as a write enable to the Channel-4 Suspend bit. The read back value of this register bit is always 0.

Value	Description
0x0	Disable Write to CH4_SUSP bit
0x1	Enable Write to respective CH4_SUSP bit

WO

0x0

CH3_SUSP_WE

This bit is used as a write enable to the Channel-3 Suspend bit. The read back value of this register bit is always 0.

Value	Description
0x0	Disable Write to CH3_SUSP bit
0x1	Enable Write to respective CH3_SUSP bit

WO

0x0

CH2_SUSP_WE

This bit is used as a write enable to the Channel-2 Suspend bit. The read back value of this register bit is always 0.

Value	Description
0x0	Disable Write to CH2_SUSP bit
0x1	Enable Write to respective CH2_SUSP bit

WO

0x0

CH1_SUSP_WE

This bit is used as a write enable to the Channel-1 Suspend bit. The read back value of this register bit is always 0.

Value	Description
0x0	Disable Write to CH1_SUSP bit
0x1	Enable Write to respective CH1_SUSP bit

WO

0x0

CH8_SUSP

Channel-8 Suspend Request.
Software sets this bit to 1 to request channel suspend. If this bit is set to 1, DW_axi_dmac suspends all DMA data transfers from the source gracefully until this bit is cleared. There is no guarantee that the current dma transaction will complete. This bit can also be used in conjunction with CH8_Status.CH_SUSPENDED to cleanly disable the channel without losing any data. In this case, software first sets CH8_SUSP bit to 1 and polls CH8_Status.CH_SUSPENDED till it is set to 1. Software can then clear CH8_EN bit to 0 to disable the channel.
 - 0: No Channel Suspend Request. 
 - 1: Request for Channel Suspend.
Software can clear CH8_SUSP bit to 0, after DW_axi_dmac sets CH8_Status.CH_SUSPENDED bit to 1, to exit the channel suspend mode.
Note: CH_SUSP is cleared when channel is
disabled.

Value	Description
0x0	No Channel Suspend Request
0x1	Request to Suspended Channel-8

RW

0x0

CH7_SUSP

Channel-7 Suspend Request.
Software sets this bit to 1 to request channel suspend. If this bit is set to 1, DW_axi_dmac suspends all DMA data transfers from the source gracefully until this bit is cleared. There is no guarantee that the current dma transaction will complete. This bit can also be used in conjunction with CH7_Status.CH_SUSPENDED to cleanly disable the channel without losing any data. In this case, software first sets CH7_SUSP bit to 1 and polls CH7_Status.CH_SUSPENDED till it is set to 1. Software can then clear CH7_EN bit to 0 to disable the channel.
 - 0: No Channel Suspend Request. 
 - 1: Request for Channel Suspend.
Software can clear CH7_SUSP bit to 0, after DW_axi_dmac sets CH7_Status.CH_SUSPENDED bit to 1, to exit the channel suspend mode.
Note: CH_SUSP is cleared when channel is
disabled.

Value	Description
0x0	No Channel Suspend Request
0x1	Request to Suspended Channel-7

RW

0x0

CH6_SUSP

Channel-6 Suspend Request.
Software sets this bit to 1 to request channel suspend. If this bit is set to 1, DW_axi_dmac suspends all DMA data transfers from the source gracefully until this bit is cleared. There is no guarantee that the current dma transaction will complete. This bit can also be used in conjunction with CH6_Status.CH_SUSPENDED to cleanly disable the channel without losing any data. In this case, software first sets CH6_SUSP bit to 1 and polls CH6_Status.CH_SUSPENDED till it is set to 1. Software can then clear CH6_EN bit to 0 to disable the channel.
 - 0: No Channel Suspend Request. 
 - 1: Request for Channel Suspend.
Software can clear CH6_SUSP bit to 0, after DW_axi_dmac sets CH6_Status.CH_SUSPENDED bit to 1, to exit the channel suspend mode.
Note: CH_SUSP is cleared when channel is
disabled.

Value	Description
0x0	No Channel Suspend Request
0x1	Request to Suspended Channel-6

RW

0x0

CH5_SUSP

Channel-5 Suspend Request.
Software sets this bit to 1 to request channel suspend. If this bit is set to 1, DW_axi_dmac suspends all DMA data transfers from the source gracefully until this bit is cleared. There is no guarantee that the current dma transaction will complete. This bit can also be used in conjunction with CH5_Status.CH_SUSPENDED to cleanly disable the channel without losing any data. In this case, software first sets CH5_SUSP bit to 1 and polls CH5_Status.CH_SUSPENDED till it is set to 1. Software can then clear CH5_EN bit to 0 to disable the channel.
 - 0: No Channel Suspend Request. 
 - 1: Request for Channel Suspend.
Software can clear CH5_SUSP bit to 0, after DW_axi_dmac sets CH5_Status.CH_SUSPENDED bit to 1, to exit the channel suspend mode.
Note: CH_SUSP is cleared when channel is
disabled.

Value	Description
0x0	No Channel Suspend Request
0x1	Request to Suspended Channel-5

RW

0x0

CH4_SUSP

Channel-4 Suspend Request.
Software sets this bit to 1 to request channel suspend. If this bit is set to 1, DW_axi_dmac suspends all DMA data transfers from the source gracefully until this bit is cleared. There is no guarantee that the current dma transaction will complete. This bit can also be used in conjunction with CH4_Status.CH_SUSPENDED to cleanly disable the channel without losing any data. In this case, software first sets CH4_SUSP bit to 1 and polls CH4_Status.CH_SUSPENDED till it is set to 1. Software can then clear CH4_EN bit to 0 to disable the channel.
 - 0: No Channel Suspend Request. 
 - 1: Request for Channel Suspend.
Software can clear CH4_SUSP bit to 0, after DW_axi_dmac sets CH4_Status.CH_SUSPENDED bit to 1, to exit the channel suspend mode.
Note: CH_SUSP is cleared when channel is
disabled.

Value	Description
0x0	No Channel Suspend Request
0x1	Request to Suspended Channel-4

RW

0x0

CH3_SUSP

Channel-3 Suspend Request.
Software sets this bit to 1 to request channel suspend. If this bit is set to 1, DW_axi_dmac suspends all DMA data transfers from the source gracefully until this bit is cleared. There is no guarantee that the current dma transaction will complete. This bit can also be used in conjunction with CH3_Status.CH_SUSPENDED to cleanly disable the channel without losing any data. In this case, software first sets CH3_SUSP bit to 1 and polls CH3_Status.CH_SUSPENDED till it is set to 1. Software can then clear CH3_EN bit to 0 to disable the channel.
 - 0: No Channel Suspend Request. 
 - 1: Request for Channel Suspend.
Software can clear CH3_SUSP bit to 0, after DW_axi_dmac sets CH3_Status.CH_SUSPENDED bit to 1, to exit the channel suspend mode.
Note: CH_SUSP is cleared when channel is
disabled.

Value	Description
0x0	No Channel Suspend Request
0x1	Request to Suspended Channel-3

RW

0x0

CH2_SUSP

Channel-2 Suspend Request.
Software sets this bit to 1 to request channel suspend. If this bit is set to 1, DW_axi_dmac suspends all DMA data transfers from the source gracefully until this bit is cleared. There is no guarantee that the current dma transaction will complete. This bit can also be used in conjunction with CH2_Status.CH_SUSPENDED to cleanly disable the channel without losing any data. In this case, software first sets CH2_SUSP bit to 1 and polls CH2_Status.CH_SUSPENDED till it is set to 1. Software can then clear CH2_EN bit to 0 to disable the channel.
 - 0: No Channel Suspend Request. 
 - 1: Request for Channel Suspend.
Software can clear CH2_SUSP bit to 0, after DW_axi_dmac sets CH2_Status.CH_SUSPENDED bit to 1, to exit the channel suspend mode.
Note: CH_SUSP is cleared when channel is
disabled.

Value	Description
0x0	No Channel Suspend Request
0x1	Request to Suspended Channel-2

RW

0x0

CH1_SUSP

Channel-1 Suspend Request.
Software sets this bit to 1 to request channel suspend. If this bit is set to 1, DW_axi_dmac suspends all DMA data transfers from the source gracefully until this bit is cleared. There is no guarantee that the current dma transaction will complete. This bit can also be used in conjunction with CH1_Status.CH_SUSPENDED to cleanly disable the channel without losing any data. In this case, software first sets CH1_SUSP bit to 1 and polls CH1_Status.CH_SUSPENDED till it is set to 1. Software can then clear CH1_EN bit to 0 to disable the channel.
 - 0: No Channel Suspend Request. 
 - 1: Request for Channel Suspend.
Software can clear CH1_SUSP bit to 0, after DW_axi_dmac sets CH1_Status.CH_SUSPENDED bit to 1, to exit the channel suspend mode.
Note: CH_SUSP is cleared when channel is
disabled.

Value	Description
0x0	No Channel Suspend Request
0x1	Request to Suspended Channel-1

RW

0x0

CH8_EN_WE

DW_axi_dmac Channel-8 Enable Write Enable bit.
Read back value of this register bit is always '0'.

Value	Description
0x0	Disable Write to respective CH8_EN bit
0x1	Enable Write to CH8_EN bit

WO

0x0

CH7_EN_WE

DW_axi_dmac Channel-7 Enable Write Enable bit.
Read back value of this register bit is always '0'.

Value	Description
0x0	Disable Write to respective CH7_EN bit
0x1	Enable Write to CH7_EN bit

WO

0x0

CH6_EN_WE

DW_axi_dmac Channel-6 Enable Write Enable bit.
Read back value of this register bit is always '0'.

Value	Description
0x0	Disable Write to respective CH6_EN bit
0x1	Enable Write to CH6_EN bit

WO

0x0

CH5_EN_WE

DW_axi_dmac Channel-5 Enable Write Enable bit.
Read back value of this register bit is always '0'.

Value	Description
0x0	Disable Write to respective CH5_EN bit
0x1	Enable Write to CH5_EN bit

WO

0x0

CH4_EN_WE

DW_axi_dmac Channel-4 Enable Write Enable bit.
Read back value of this register bit is always '0'.

Value	Description
0x0	Disable Write to respective CH4_EN bit
0x1	Enable Write to CH4_EN bit

WO

0x0

CH3_EN_WE

DW_axi_dmac Channel-3 Enable Write Enable bit.
Read back value of this register bit is always '0'.

Value	Description
0x0	Disable Write to respective CH3_EN bit
0x1	Enable Write to CH3_EN bit

WO

0x0

CH2_EN_WE

DW_axi_dmac Channel-2 Enable Write Enable bit.
Read back value of this register bit is always '0'.

Value	Description
0x0	Disable Write to respective CH2_EN bit
0x1	Enable Write to CH2_EN bit

WO

0x0

CH1_EN_WE

DW_axi_dmac Channel-1 Enable Write Enable bit.
Read back value of this register bit is always '0'.

Value	Description
0x0	Disable Write to respective CH1_EN bit
0x1	Enable Write to CH1_EN bit

WO

0x0

CH8_EN

This bit is used to enable the DW_axi_dmac Channel-8.
 - 0: DW_axi_dmac Channel-8 is disabled
 - 1: DW_axi_dmac Channel-8 is enabled
The bit 'DMAC_ChEnReg.CH8_EN' is automatically cleared by hardware to disable the channel after the last AMBA transfer of the DMA transfer to the destination has completed. Software can therefore poll this bit to determine when this channel is free for a new DMA transfer.

Value	Description
0x0	DW_axi_dmac: Channel-8 is disabled
0x1	DW_axi_dmac: Channel-8 is enabled

RW

0x0

CH7_EN

This bit is used to enable the DW_axi_dmac Channel-7.
 - 0: DW_axi_dmac Channel-7 is disabled
 - 1: DW_axi_dmac Channel-7 is enabled
The bit 'DMAC_ChEnReg.CH7_EN' is automatically cleared by hardware to disable the channel after the last AMBA transfer of the DMA transfer to the destination has completed. Software can therefore poll this bit to determine when this channel is free for a new DMA transfer.

Value	Description
0x0	DW_axi_dmac: Channel-7 is disabled
0x1	DW_axi_dmac: Channel-7 is enabled

RW

0x0

CH6_EN

This bit is used to enable the DW_axi_dmac Channel-6.
 - 0: DW_axi_dmac Channel-6 is disabled
 - 1: DW_axi_dmac Channel-6 is enabled
The bit 'DMAC_ChEnReg.CH6_EN' is automatically cleared by hardware to disable the channel after the last AMBA transfer of the DMA transfer to the destination has completed. Software can therefore poll this bit to determine when this channel is free for a new DMA transfer.

Value	Description
0x0	DW_axi_dmac: Channel-6 is disabled
0x1	DW_axi_dmac: Channel-6 is enabled

RW

0x0

CH5_EN

This bit is used to enable the DW_axi_dmac Channel-5.
 - 0: DW_axi_dmac Channel-5 is disabled
 - 1: DW_axi_dmac Channel-5 is enabled
The bit 'DMAC_ChEnReg.CH5_EN' is automatically cleared by hardware to disable the channel after the last AMBA transfer of the DMA transfer to the destination has completed. Software can therefore poll this bit to determine when this channel is free for a new DMA transfer.

Value	Description
0x0	DW_axi_dmac: Channel-5 is disabled
0x1	DW_axi_dmac: Channel-5 is enabled

RW

0x0

CH4_EN

This bit is used to enable the DW_axi_dmac Channel-4.
 - 0: DW_axi_dmac Channel-4 is disabled
 - 1: DW_axi_dmac Channel-4 is enabled
The bit 'DMAC_ChEnReg.CH4_EN' is automatically cleared by hardware to disable the channel after the last AMBA transfer of the DMA transfer to the destination has completed. Software can therefore poll this bit to determine when this channel is free for a new DMA transfer.

Value	Description
0x0	DW_axi_dmac: Channel-4 is disabled
0x1	DW_axi_dmac: Channel-4 is enabled

RW

0x0

CH3_EN

This bit is used to enable the DW_axi_dmac Channel-3.
 - 0: DW_axi_dmac Channel-3 is disabled
 - 1: DW_axi_dmac Channel-3 is enabled
The bit 'DMAC_ChEnReg.CH3_EN' is automatically cleared by hardware to disable the channel after the last AMBA transfer of the DMA transfer to the destination has completed. Software can therefore poll this bit to determine when this channel is free for a new DMA transfer.

Value	Description
0x0	DW_axi_dmac: Channel-3 is disabled
0x1	DW_axi_dmac: Channel-3 is enabled

RW

0x0

CH2_EN

This bit is used to enable the DW_axi_dmac Channel-2.
 - 0: DW_axi_dmac Channel-2 is disabled
 - 1: DW_axi_dmac Channel-2 is enabled
The bit 'DMAC_ChEnReg.CH2_EN' is automatically cleared by hardware to disable the channel after the last AMBA transfer of the DMA transfer to the destination has completed. Software can therefore poll this bit to determine when this channel is free for a new DMA transfer.

Value	Description
0x0	DW_axi_dmac: Channel-2 is disabled
0x1	DW_axi_dmac: Channel-2 is enabled

RW

0x0

CH1_EN

This bit is used to enable the DW_axi_dmac Channel-1.
 - 0: DW_axi_dmac Channel-1 is disabled
 - 1: DW_axi_dmac Channel-1 is enabled
The bit 'DMAC_ChEnReg.CH1_EN' is automatically cleared by hardware to disable the channel after the last AMBA transfer of the DMA transfer to the destination has completed. Software can therefore poll this bit to determine when this channel is free for a new DMA transfer.

Value	Description
0x0	DW_axi_dmac: Channel-1 is disabled
0x1	DW_axi_dmac: Channel-1 is enabled

RW

0x0