DMAC_LOWPOWER_CFGREG

         This register contains the fields that configures the Context Sensitive Low Power feature. This register should be programmed prior to enabling the channel.


Module Instance	Base Address	Register Address
`i_dma__dmac1_ahb_slv__10dc0000__Common_Registers_Address_Block__SEG_L4_AHB_dmac1_s_0x0_0x10000`	`0x10DC0000`	`0x10DC0060`

Size: 64

Offset: 0x60

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
`RSVD_DMAC_LOWPOWER_CFGREG_63to56` `RO 0x0`								`MXIF_LPDLY` `RW 0x0`
47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
`SBIU_LPDLY` `RW 0x0`								`GLCH_LPDLY` `RW 0x0`
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`RSVD_DMAC_LOWPOWER_CFGREG_31to4` `RO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`RSVD_DMAC_LOWPOWER_CFGREG_31to4` `RO 0x0`												`MXIF_CSLP_EN` `RW 0x0`	`SBIU_CSLP_EN` `RW 0x0`	`CHNL_CSLP_EN` `RW 0x0`	`GBL_CSLP_EN` `RW 0x0`

DMAC_LOWPOWER_CFGREG Fields

Bit Name Description Access Reset

63:56

RSVD_DMAC_LOWPOWER_CFGREG_63to56

DMAC_LOWPOWER_CFGREG (bits 56to63) Reserved bits - Read Only

RO

0x0

55:48

MXIF_LPDLY

Defines the load value to be programmed into the AXI Master Interface low power delay counter. 
The programmed value must be greater than or equal to 0x4. If value programmed is less than 0x4, 
then the register value is reset to DMAX_MXIF_LPDLY. The maximum value programmed into this 
register field is limited to (2**DMAX_MXIF_LPDLY_WIDTH)-1, otherwise the upper bits (8-DMAX_MXIF_LPDLY_WIDTH) 
of this field is reset to 0x0.

RW

0x0

47:40

SBIU_LPDLY

Defines the load value to be programmed into the SBIU low power delay counter. 
The programmed value must be greater than or equal to 0x4. If value programmed is less than 0x4, 
then the register value is reset to DMAX_SBIU_LPDLY. The maximum value programmed into this 
register field is limited to (2**DMAX_SBIU_LPDLY_WIDTH)-1, otherwise the upper bits (8-DMAX_SBIU_LPDLY_WIDTH) 
of this field is reset to 0x0.

RW

0x0

39:32

GLCH_LPDLY

Defines the load value to be programmed into the Global and DMA Channel low power delay counter. 
The programmed value must be greater than or equal to 0x4. If value programmed is less than 0x4, 
then the register value is reset to DMAX_GLCH_LPDLY. The maximum value programmed into this 
register field is limited to (2**DMAX_GLCH_LPDLY_WIDTH)-1, otherwise the upper bits (8-DMAX_GLCH_LPDLY_WIDTH) 
of this field is reset to 0x0.

RW

0x0

31:4

RSVD_DMAC_LOWPOWER_CFGREG_31to4

DMAC_LOWPOWER_CFGREG (bits 4to31) Reserved bits - Read Only

RO

0x0

MXIF_CSLP_EN

AXI Master Interface Context Sensitive Low Power feature enable.

Value	Description
0x0	AXI Master Interface Context Sensitive Low Power feature is disabled
0x1	AXI Master Interface Context Sensitive Low Power feature is enabled

RW

0x0

SBIU_CSLP_EN

SBIU Context Sensitive Low Power feature enable.

Value	Description
0x0	SBIU Context Sensitive Low Power feature is disabled
0x1	SBIU Context Sensitive Low Power feature is enabled

RW

0x0

CHNL_CSLP_EN

DMA Channel Context Sensitive Low Power feature enable.

Value	Description
0x0	DMA Channel Context Sensitive Low Power feature is disabled
0x1	DMA Channel Context Sensitive Low Power feature is enabled

RW

0x0

GBL_CSLP_EN

Global Context Sensitive Low Power feature enable.

Value	Description
0x0	Global Context Sensitive Low Power feature is disabled
0x1	Global Context Sensitive Low Power feature is enabled

RW

0x0