CCU_DSU Summary

Base Address: 0x1C000000


Register Address Offset	Bit Fields
`i_ccu__DSU__1c000000__DSU`
`CAIUIDR` `0x0` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Valid` `RO 0x1`	`Rsvd1` `RO 0x0`							`NUnitId` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`NUnitId` `RO 0x0`				`NRRI` `RO 0x0`				`RPN` `RO 0x0`
`CAIUFUIDR` `0x4` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Rsvd1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`FUnitId` `RO 0x0`
`CAIUTCR` `0x64` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Rsvd3` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd3` `RO 0x0`						`SysCoAttach` `RW 0x0`	`SysCoDisable` `RW 0x0`	`Rsvd2` `RO 0x0`			`EventDisable` `RW 0x0`	`Rsvd1` `RO 0x0`			`RDisable` `RW 0x0`
`CAIUTAR` `0x68` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Rsvd2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd2` `RO 0x0`									`SysCoError` `RO 0x0`	`SysCoAttached` `RO 0x0`	`SysCoConnecting` `RO 0x0`	`Rsvd1` `RO 0x0`			`TransActv` `RO 0x0`
`CAIUUEDR` `0x256` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Rsvd1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd1` `RO 0x0`											`TimeoutErrDetEn` `RW 0x0`	`DecErrDetEn` `RW 0x0`	`MemErrDetEn` `RW 0x0`	`TransErrDetEn` `RW 0x0`	`ProtErrDetEn` `RW 0x0`
`CAIUUEIR` `0x260` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Rsvd1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd1` `RO 0x0`											`TimeOutErrIntEn` `RW 0x0`	`DecErrIntEn` `RW 0x0`	`MemErrIntEn` `RW 0x0`	`TransErrIntEn` `RW 0x0`	`ProtErrIntEn` `RW 0x0`
`CAIUUESR` `0x264` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`ErrInfo` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd2` `RO 0x0`								`ErrType` `RO 0x0`				`Rsvd1` `RO 0x0`			`ErrVld` `RW 0x0`
`CAIUUELR0` `0x268` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`ErrWord` `RW 0x0`						`ErrWay` `RW 0x0`						`ErrEntry` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ErrEntry` `RW 0x0`
`CAIUUELR1` `0x272` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Rsvd1` `RO 0x0`												`ErrAddr` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ErrAddr` `RW 0x0`
`CAIUUESAR` `0x276` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`ErrInfo` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd2` `RO 0x0`								`ErrType` `RW 0x0`				`Rsvd1` `RO 0x0`			`ErrVld` `RW 0x0`
`CAIUCRTR` `0x384` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Rsvd1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd1` `RO 0x0`								`ResThreshold` `RW 0x1`
`CAIUTOCR` `0x400` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`TimeOutRefEn` `RW 0x0`	`TimeOutThreshold` `RW 0x4000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`TimeOutThreshold` `RW 0x4000`
`CAIUQOSCR` `0x512` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Rsvd1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`EventThreshold` `RW 0x40`
`CAIUQOSSR` `0x516` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Rsvd2` `RO 0x0`												`EventStatusCount` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`EventStatusCount` `RW 0x0`												`Rsvd1` `RO 0x0`		`EventStatusCountOverflow` `RW 0x0`	`EventStatus` `RO 0x0`
`NRSBAR` `0x896` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`NRSBA` `RW 0x1C0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`NRSBA` `RW 0x1C0`
`NRSBHR` `0x900` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`NRSBA` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`NRSBA` `RW 0x0`
`NRSBLR` `0x904` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BALoaded` `RW 0x0`	`Rsvd2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd2` `RO 0x0`		`NRSDIIId` `RW 0x0`										`Rsvd1` `RO 0x0`			`Secure` `RW 0x0`
`CAIUBRAR` `0x912` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Valid` `RW 0x1`	`HUT` `RW 0x1`	`Rsvd3` `RO 0x0`					`Size` `RW 0x7`					`Rsvd2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd2` `RO 0x0`		`HUI` `RW 0x3`					`Rsvd1` `RO 0x0`
`CAIUBRBLR` `0x916` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`AddrLow` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`AddrLow` `RW 0x0`
`CAIUBRBHR` `0x920` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Rsvd1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd1` `RO 0x0`								`AddrHigh` `RW 0x0`
`CAIUAMIGR` `0x960` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Rsvd1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd1` `RO 0x0`											`AMIGS` `RW 0x0`				`Valid` `RW 0x0`
`CAIUMIFSR` `0x964` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Rsvd5` `RO 0x0`					`MIG16AIFId` `RW 0x0`			`Rsvd4` `RO 0x0`					`MIG8AIFId` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd3` `RO 0x0`					`MIG4AIFId` `RW 0x0`			`Rsvd2` `RO 0x0`	`MIG3AIFId` `RW 0x0`			`Rsvd1` `RO 0x0`	`MIG2AIFId` `RW 0x0`
`CAIUGPRAR0` `0x1024` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Valid` `RW 0x0`	`HUT` `RW 0x0`	`Rsvd3` `RO 0x0`					`Size` `RW 0x0`					`Rsvd2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd2` `RO 0x0`		`HUI` `RW 0x0`					`Rsvd1` `RO 0x0`				`Policy` `RW 0x0`		`WriteID` `RW 0x0`	`ReadID` `RW 0x0`	`Hazard` `RW 0x0`
`CAIUGPRBLR0` `0x1028` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`AddrLow` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`AddrLow` `RW 0x0`
`CAIUGPRBHR0` `0x1032` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Rsvd1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd1` `RO 0x0`								`AddrHigh` `RW 0x0`
`CAIUGPRAR1` `0x1040` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Valid` `RW 0x0`	`HUT` `RW 0x0`	`Rsvd3` `RO 0x0`					`Size` `RW 0x0`					`Rsvd2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd2` `RO 0x0`		`HUI` `RW 0x0`					`Rsvd1` `RO 0x0`				`Policy` `RW 0x0`		`WriteID` `RW 0x0`	`ReadID` `RW 0x0`	`Hazard` `RW 0x0`
`CAIUGPRBLR1` `0x1044` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`AddrLow` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`AddrLow` `RW 0x0`
`CAIUGPRBHR1` `0x1048` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Rsvd1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd1` `RO 0x0`								`AddrHigh` `RW 0x0`
`CAIUGPRAR2` `0x1056` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Valid` `RW 0x0`	`HUT` `RW 0x0`	`Rsvd3` `RO 0x0`					`Size` `RW 0x0`					`Rsvd2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd2` `RO 0x0`		`HUI` `RW 0x0`					`Rsvd1` `RO 0x0`				`Policy` `RW 0x0`		`WriteID` `RW 0x0`	`ReadID` `RW 0x0`	`Hazard` `RW 0x0`
`CAIUGPRBLR2` `0x1060` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`AddrLow` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`AddrLow` `RW 0x0`
`CAIUGPRBHR2` `0x1064` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Rsvd1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd1` `RO 0x0`								`AddrHigh` `RW 0x0`
`CAIUGPRAR3` `0x1072` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Valid` `RW 0x0`	`HUT` `RW 0x0`	`Rsvd3` `RO 0x0`					`Size` `RW 0x0`					`Rsvd2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd2` `RO 0x0`		`HUI` `RW 0x0`					`Rsvd1` `RO 0x0`				`Policy` `RW 0x0`		`WriteID` `RW 0x0`	`ReadID` `RW 0x0`	`Hazard` `RW 0x0`
`CAIUGPRBLR3` `0x1076` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`AddrLow` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`AddrLow` `RW 0x0`
`CAIUGPRBHR3` `0x1080` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Rsvd1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd1` `RO 0x0`								`AddrHigh` `RW 0x0`
`CAIUGPRAR4` `0x1088` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Valid` `RW 0x0`	`HUT` `RW 0x0`	`Rsvd3` `RO 0x0`					`Size` `RW 0x0`					`Rsvd2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd2` `RO 0x0`		`HUI` `RW 0x0`					`Rsvd1` `RO 0x0`				`Policy` `RW 0x0`		`WriteID` `RW 0x0`	`ReadID` `RW 0x0`	`Hazard` `RW 0x0`
`CAIUGPRBLR4` `0x1092` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`AddrLow` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`AddrLow` `RW 0x0`
`CAIUGPRBHR4` `0x1096` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Rsvd1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd1` `RO 0x0`								`AddrHigh` `RW 0x0`
`CAIUGPRAR5` `0x1104` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Valid` `RW 0x0`	`HUT` `RW 0x0`	`Rsvd3` `RO 0x0`					`Size` `RW 0x0`					`Rsvd2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd2` `RO 0x0`		`HUI` `RW 0x0`					`Rsvd1` `RO 0x0`				`Policy` `RW 0x0`		`WriteID` `RW 0x0`	`ReadID` `RW 0x0`	`Hazard` `RW 0x0`
`CAIUGPRBLR5` `0x1108` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`AddrLow` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`AddrLow` `RW 0x0`
`CAIUGPRBHR5` `0x1112` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Rsvd1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd1` `RO 0x0`								`AddrHigh` `RW 0x0`
`CAIUGPRAR6` `0x1120` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Valid` `RW 0x0`	`HUT` `RW 0x0`	`Rsvd3` `RO 0x0`					`Size` `RW 0x0`					`Rsvd2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd2` `RO 0x0`		`HUI` `RW 0x0`					`Rsvd1` `RO 0x0`				`Policy` `RW 0x0`		`WriteID` `RW 0x0`	`ReadID` `RW 0x0`	`Hazard` `RW 0x0`
`CAIUGPRBLR6` `0x1124` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`AddrLow` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`AddrLow` `RW 0x0`
`CAIUGPRBHR6` `0x1128` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Rsvd1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd1` `RO 0x0`								`AddrHigh` `RW 0x0`
`CAIUGPRAR7` `0x1136` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Valid` `RW 0x0`	`HUT` `RW 0x0`	`Rsvd3` `RO 0x0`					`Size` `RW 0x0`					`Rsvd2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd2` `RO 0x0`		`HUI` `RW 0x0`					`Rsvd1` `RO 0x0`				`Policy` `RW 0x0`		`WriteID` `RW 0x0`	`ReadID` `RW 0x0`	`Hazard` `RW 0x0`
`CAIUGPRBLR7` `0x1140` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`AddrLow` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`AddrLow` `RW 0x0`
`CAIUGPRBHR7` `0x1144` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Rsvd1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd1` `RO 0x0`								`AddrHigh` `RW 0x0`
`CAIUGPRAR8` `0x1152` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Valid` `RW 0x0`	`HUT` `RW 0x0`	`Rsvd3` `RO 0x0`					`Size` `RW 0x0`					`Rsvd2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd2` `RO 0x0`		`HUI` `RW 0x0`					`Rsvd1` `RO 0x0`				`Policy` `RW 0x0`		`WriteID` `RW 0x0`	`ReadID` `RW 0x0`	`Hazard` `RW 0x0`
`CAIUGPRBLR8` `0x1156` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`AddrLow` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`AddrLow` `RW 0x0`
`CAIUGPRBHR8` `0x1160` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Rsvd1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd1` `RO 0x0`								`AddrHigh` `RW 0x0`
`CAIUGPRAR9` `0x1168` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Valid` `RW 0x0`	`HUT` `RW 0x0`	`Rsvd3` `RO 0x0`					`Size` `RW 0x0`					`Rsvd2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd2` `RO 0x0`		`HUI` `RW 0x0`					`Rsvd1` `RO 0x0`				`Policy` `RW 0x0`		`WriteID` `RW 0x0`	`ReadID` `RW 0x0`	`Hazard` `RW 0x0`
`CAIUGPRBLR9` `0x1172` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`AddrLow` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`AddrLow` `RW 0x0`
`CAIUGPRBHR9` `0x1176` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Rsvd1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd1` `RO 0x0`								`AddrHigh` `RW 0x0`
`CAIUGPRAR10` `0x1184` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Valid` `RW 0x0`	`HUT` `RW 0x0`	`Rsvd3` `RO 0x0`					`Size` `RW 0x0`					`Rsvd2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd2` `RO 0x0`		`HUI` `RW 0x0`					`Rsvd1` `RO 0x0`				`Policy` `RW 0x0`		`WriteID` `RW 0x0`	`ReadID` `RW 0x0`	`Hazard` `RW 0x0`
`CAIUGPRBLR10` `0x1188` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`AddrLow` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`AddrLow` `RW 0x0`
`CAIUGPRBHR10` `0x1192` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Rsvd1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd1` `RO 0x0`								`AddrHigh` `RW 0x0`
`CAIUGPRAR11` `0x1200` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Valid` `RW 0x0`	`HUT` `RW 0x0`	`Rsvd3` `RO 0x0`					`Size` `RW 0x0`					`Rsvd2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd2` `RO 0x0`		`HUI` `RW 0x0`					`Rsvd1` `RO 0x0`				`Policy` `RW 0x0`		`WriteID` `RW 0x0`	`ReadID` `RW 0x0`	`Hazard` `RW 0x0`
`CAIUGPRBLR11` `0x1204` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`AddrLow` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`AddrLow` `RW 0x0`
`CAIUGPRBHR11` `0x1208` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Rsvd1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd1` `RO 0x0`								`AddrHigh` `RW 0x0`
`CAIUCCTRLR` `0x2304` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`inc` `RW 0x100`												`gain` `RW 0x2`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd` `RO 0x0`								`dn0Rx` `RW 0x0`	`dn0Tx` `RW 0x0`	`ndn2Rx` `RW 0x0`	`ndn2Tx` `RW 0x0`	`ndn1Rx` `RW 0x0`	`ndn1Tx` `RW 0x0`	`ndn0Rx` `RW 0x0`	`ndn0Tx` `RW 0x0`
`CAIUTCTRLR0` `0x2308` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`memattr` `RW 0x0`				`Rsvd2` `RO 0x0`				`range` `RW 0x0`					`Rsvd1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd1` `RO 0x0`				`hui` `RW 0x0`					`hut` `RW 0x0`	`target_type_match_en` `RW 0x0`	`user_match_en` `RW 0x0`	`memattr_match_en` `RW 0x0`	`opcode_match_en` `RW 0x0`	`addr_match_en` `RW 0x0`	`native_trace_en` `RW 0x1`
`CAIUTBALR0` `0x2312` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`base_addr_lo` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`base_addr_lo` `RW 0x0`
`CAIUTBAHR0` `0x2316` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Rsvd1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd1` `RO 0x0`								`base_addr_hi` `RW 0x0`
`CAIUTOPCR00` `0x2320` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`valid2` `RW 0x0`	`Rsvd2` `RO 0x0`									`opcode2` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`valid1` `RW 0x0`	`Rsvd1` `RO 0x0`									`opcode1` `RW 0x0`
`CAIUTOPCR10` `0x2324` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`valid4` `RW 0x0`	`Rsvd2` `RO 0x0`									`opcode4` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`valid3` `RW 0x0`	`Rsvd1` `RO 0x0`									`opcode3` `RW 0x0`
`CAIUTUBR0` `0x2328` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Rsvd1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd1` `RO 0x0`												`user` `RW 0x0`
`CAIUTUBMR0` `0x2332` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Rsvd1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd1` `RO 0x0`												`user_mask` `RW 0x0`
`CAIUCNTCR0` `0x2816` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Rsvd1` `RO 0x0`		`CntEvtFirst` `RW 0x0`						`Rsvd0` `RO 0x0`		`CntEvtSecond` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MinStallPeriod` `RW 0x0`			`FilterSel` `RW 0x0`			`SSRCount` `RW 0x0`			`CounterCtl` `RW 0x0`			`OverFlowStatus` `RO 0x0`	`InterruptEn` `RW 0x0`	`CountClr` `RW 0x0`	`CountEn` `RW 0x0`
`CAIUCNTVR0` `0x2820` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`CountVal` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`CountVal` `RW 0x0`
`CAIUCNTSR0` `0x2824` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`CountSatVal` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`CountSatVal` `RW 0x0`
`CAIUCNTCR1` `0x2832` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Rsvd1` `RO 0x0`		`CntEvtFirst` `RW 0x0`						`Rsvd0` `RO 0x0`		`CntEvtSecond` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MinStallPeriod` `RW 0x0`			`FilterSel` `RW 0x0`			`SSRCount` `RW 0x0`			`CounterCtl` `RW 0x0`			`OverFlowStatus` `RO 0x0`	`InterruptEn` `RW 0x0`	`CountClr` `RW 0x0`	`CountEn` `RW 0x0`
`CAIUCNTVR1` `0x2836` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`CountVal` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`CountVal` `RW 0x0`
`CAIUCNTSR1` `0x2840` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`CountSatVal` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`CountSatVal` `RW 0x0`
`CAIUCNTCR2` `0x2848` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Rsvd1` `RO 0x0`		`CntEvtFirst` `RW 0x0`						`Rsvd0` `RO 0x0`		`CntEvtSecond` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MinStallPeriod` `RW 0x0`			`FilterSel` `RW 0x0`			`SSRCount` `RW 0x0`			`CounterCtl` `RW 0x0`			`OverFlowStatus` `RO 0x0`	`InterruptEn` `RW 0x0`	`CountClr` `RW 0x0`	`CountEn` `RW 0x0`
`CAIUCNTVR2` `0x2852` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`CountVal` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`CountVal` `RW 0x0`
`CAIUCNTSR2` `0x2856` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`CountSatVal` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`CountSatVal` `RW 0x0`
`CAIUCNTCR3` `0x2864` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Rsvd1` `RO 0x0`		`CntEvtFirst` `RW 0x0`						`Rsvd0` `RO 0x0`		`CntEvtSecond` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MinStallPeriod` `RW 0x0`			`FilterSel` `RW 0x0`			`SSRCount` `RW 0x0`			`CounterCtl` `RW 0x0`			`OverFlowStatus` `RO 0x0`	`InterruptEn` `RW 0x0`	`CountClr` `RW 0x0`	`CountEn` `RW 0x0`
`CAIUCNTVR3` `0x2868` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`CountVal` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`CountVal` `RW 0x0`
`CAIUCNTSR3` `0x2872` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`CountSatVal` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`CountSatVal` `RW 0x0`
`CAIUNRSAR` `0x4080` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Rsvd1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd1` `RO 0x0`															`NRSAR` `RW 0x1`
`CAIUUEVIR` `0x4084` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`EngVerId` `RO 0xB92A000B`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`EngVerId` `RO 0xB92A000B`
`CAIUINFOR` `0x4092` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Valid` `RO 0x1`	`Rsvd1` `RO 0x0`												`UST` `RO 0x2`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UT` `RO 0x0`				`ImplVer` `RO 0x323`