CAIUTCR
AIU Transaction Control Register
Module Instance | Base Address | Register Address |
---|---|---|
i_ccu__DSU__1c000000__DSU
|
0x1C000000
|
0x1C000040
|
Size: 32
Offset: 0x40
Access: RO
Bit Fields | |||||||||||||||
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31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
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15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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CAIUTCR Fields
Bit | Name | Description | Access | Reset |
---|---|---|---|---|
31:10 |
Rsvd3
|
Reserved |
RO
|
0x0
|
9 |
SysCoAttach
|
Writing 1 to this bit when the status register bit SysCoAttached is 0 starts an attach sequence. Writing 0 to this bit when the status register bit SysCoAttached is 1 starts a detach sequence. |
RW
|
0x0
|
8 |
SysCoDisable
|
Setting this disables SysCo. |
RW
|
0x0
|
7:5 |
Rsvd2
|
Reserved |
RO
|
0x0
|
4 |
EventDisable
|
Setting this disables Event handling. |
RW
|
0x0
|
3:1 |
Rsvd1
|
Reserved |
RO
|
0x0
|
0 |
RDisable
|
This controls whether new requests can be accepted inside the AIU. |
RW
|
0x0
|