CAIUTCTRLR0 

         XAIU Trace Trigger Control Register
Module Instance Base Address Register Address
i_ccu__DSU__1c000000__DSU 0x1C000000 0x1C000904

Size: 32

Offset: 0x904

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

memattr

RW 0x0

Rsvd2

RO 0x0

range

RW 0x0

Rsvd1

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Rsvd1

RO 0x0

hui

RW 0x0

hut

RW 0x0

target_type_match_en

RW 0x0

user_match_en

RW 0x0

memattr_match_en

RW 0x0

opcode_match_en

RW 0x0

addr_match_en

RW 0x0

native_trace_en

RW 0x1

CAIUTCTRLR0 Fields

Bit Name Description Access Reset
31:28 memattr 
Specifies memory attribute. Memattr on CHI, AxCache on AXI/ACE/ACE-Lite/ACE-Lite-E
 RW 0x0
27:24 Rsvd2 
Reserved
 RO 0x0
23:19 range 
Address range size. This field indicates a binary number from 0 to 31 from which region's size is calculated as (Size of IG) * 2^(Size + 12) bytes
 RW 0x0
18:12 Rsvd1 
Reserved
 RO 0x0
11:7 hui 
Specifies the HUI NunItID for DII, and MIG number for DMI
 RW 0x0
6 hut 
Specify target type. 0: DMI, 1: DII
 RW 0x0
5 target_type_match_en 
Enable Trace if there is a match on specified target type
 RW 0x0
4 user_match_en 
Enable Trace if there is a match on specified user bits
 RW 0x0
3 memattr_match_en 
Enable Trace on memory attribute match
 RW 0x0
2 opcode_match_en 
Enable Trace on opcode match
 RW 0x0
1 addr_match_en 
Enable Trace on address range match
 RW 0x0
0 native_trace_en 
0: Ignore native trace signaling. 1: Allow native trace signaling to set trigger
 RW 0x1