CAIUUESR

         AIU Uncorrectable Error Status Register


Module Instance	Base Address	Register Address
`i_ccu__DSU__1c000000__DSU`	`0x1C000000`	`0x1C000108`

Size: 32

Offset: 0x108

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`ErrInfo` `RO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Rsvd2` `RO 0x0`								`ErrType` `RO 0x0`				`Rsvd1` `RO 0x0`			`ErrVld` `RW 0x0`

CAIUUESR Fields


Bit	Name	Description	Access	Reset
31:16	`ErrInfo`	This field indicates additional information about logged error type, if the Uncorrectable Error Valid bit is set. If it is a native interface write response error then bits 1:0 Response from the interface bit 2 Security attribute bits 15:3 Reserved If it is a native interface read response error then bits 1:0 Response from the interface bit 2 Security attribute bits 15:3 Reserved If it is a native interface snoop response error then bits 1:0 Response from the interface bit 2 Security attribute bits 15:3 Reserved If it is a decode error then bits 1:0 Represent type of decode error 2'b00: No address region hit 2'b01: Multiple address region hit 2'b10: Illegal CSR acess format 2'b11: Illegal DII access type bits 5:2 Reserved bits 15:6 Transaction ID If it is a transport error then bit 0 1'b0 represents wrong target ID; 1'b1 Reserved bits 5:1 Reserved bits 15:6 Represents source ID If it is a time out error then bits 1:0 Reserved bit 2 Represents the security bit bits 15:3 Reserved	`RO`	`0x0`
15:8	`Rsvd2`	Reserved	`RO`	`0x0`
7:4	`ErrType`	This field indicates the logged error type, if the Uncorrectable Error Valid bit is set. 0x02: Native interface write response error 0x03: Native interface read response error 0x04: Native interface snoop response error 0x07: Decode error 0x08: Transport error 0x09: Timeout error All other encodings are reserved	`RO`	`0x0`
3:1	`Rsvd1`	Reserved	`RO`	`0x0`
0	`ErrVld`	If this bit is set, Error information is logged in status and location registers. Writing a one to the Uncorrectable Error Valid bit clears the Correctable Error Valid bit.	`RW`	`0x0`