CAIUUEIR 

         CAIU Uncorrectable Error Interrupt Register
Module Instance Base Address Register Address
i_ccu__DSU__1c000000__DSU 0x1C000000 0x1C000104

Size: 32

Offset: 0x104

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Rsvd1

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Rsvd1

RO 0x0

TimeOutErrIntEn

RW 0x0

DecErrIntEn

RW 0x0

MemErrIntEn

RW 0x0

TransErrIntEn

RW 0x0

ProtErrIntEn

RW 0x0

CAIUUEIR Fields

Bit Name Description Access Reset
31:5 Rsvd1 
Reserved
 RO 0x0
4 TimeOutErrIntEn 
Time Out Error Interrupt Enable. When set to 1, this bit enables the assertion of Time Out Error Interrupt signal.
RW 0x0
3 DecErrIntEn 
Decode Error Interrupt Enable. When set, this bit enables the assertion of address map Uncorrectable Error Interrupt signal.
 RW 0x0
2 MemErrIntEn 
Memory protection error interrupt enable: When set, errors will be detected from any RAM memory arrays.
 RW 0x0
1 TransErrIntEn 
Concerto Transport error interrupt enable: When set, errors will be detected from the Concerto Transport.
 RW 0x0
0 ProtErrIntEn 
Downstream AXI uncorrectable error interrupt enable.
 RW 0x0