Triple-Speed Ethernet Intel® FPGA IP

Triple-Speed Ethernet Intel® FPGA IP

Ordering Information
Ordering code

IP-TRIETHERNET: Triple-Speed Ethernet

IP-TRIETHERNETF: IEEE 1588v2 for Triple-Speed Ethernet

IP Quality Metrics

Basics

1588 v2 option

Year IP was first released as Intel FPGA IP

2017

2017

First version of Intel Quartus Prime software support

17.2

17.2

Status

Production

Production

Deliverables

1588 v2 option

Customer deliverables include the following:

Design file (encrypted source code or post-synthesis netlist)

Simulation model for ModelSim*-Intel FPGA Edition

Timing and/or layout constraints

Documentation with revision control

Readme file

Y

Y

Any additional customer deliverables provided with IP

 

 

Parameterization GUI allowing end user to configure IP

Y

Y

IP core is enabled for Intel FPGA IP Evaluation Mode Support

Y

Y

Source language

Verilog

Verilog

Testbench language

 

 

Software drivers provided

 N

N

Driver OS Support

 

 

Implementation

1588 v2 option

User interface

MII (10/100 Mb) GMII or RGMII (1000 Mbps)

MII (10/100 Mb) GMII or RGMII (1000 Mbps)

IP-XACT metadata

N

N

Verification

1588 v2 option

Simulators supported

Mentor Graphics*, Synopsys*, Cadence*

Mentor Graphics*, Synopsys*, Cadence*

Hardware validated

Intel Arria 10, Intel Stratix 10, Intel Cyclone 10 GX

Intel Arria 10, Intel Cyclone 10 GX

Industry-standard compliance testing performed

UNH IEEE 802.3 compliance  

UNH IEEE 802.3 for MAC/PH, N/A for 1588 option.   

If Yes, which test(s)?

Clause 4, 46, 31 and 49

Clause 4, 46, 31, and 49

If Yes, on which Intel FPGA (s)?

Intel Arria 10

Intel Arria 10

If Yes, date performed

2011

2012

If No, is it planned?

 

 

Interoperability

1588 v2 option

IP has undergone interoperability testing

N

N

If yes, on which Intel FPGA (s)

 

 

Interoperability reports available

N

N