Skip To Main Content
Intel logo - Return to the home page
My Tools

Select Your Language

  • Bahasa Indonesia
  • Deutsch
  • English
  • Español
  • Français
  • Português
  • Tiếng Việt
  • ไทย
  • 한국어
  • 日本語
  • 简体中文
  • 繁體中文
Sign In to access restricted content

Using Intel.com Search

You can easily search the entire Intel.com site in several ways.

  • Brand Name: Core i9
  • Document Number: 123456
  • Code Name: Emerald Rapids
  • Special Operators: “Ice Lake”, Ice AND Lake, Ice OR Lake, Ice*

Quick Links

You can also try the quick links below to see results for most popular searches.

  • Product Information
  • Support
  • Drivers & Software

Recent Searches

Sign In to access restricted content

Advanced Search

Only search in

Sign in to access restricted content.
  1. Intel® Products
  2. Altera® FPGA, SoC FPGA and CPLD
  3. Altera® FPGA Intellectual Property
  4. Interface Protocols IP Cores
  5. Low Latency Ethernet 10G MAC FPGA IP

The browser version you are using is not recommended for this site.
Please consider upgrading to the latest version of your browser by clicking one of the following links.

  • Safari
  • Chrome
  • Edge
  • Firefox

Low Latency Ethernet 10G MAC FPGA IP

The Low Latency Ethernet 10G MAC FPGA IP core (soft IP) offers low round-trip latency, and an efficient resource footprint. The Intellectual Property (IP) core offers programmability of various features listed. This IP can be used in conjunction with the new Multi-Rate PHY FPGA IP core to support the range of 10M/100M/1G to 10G data rates.

Read the Low Latency Ethernet 10G MAC FPGA IP user guide ›

Read the 10-Gbps Ethernet MAC MegaCore Function user guide ›

Read the Low Latency Ethernet 10G MAC Agilex™ 5 FPGA IP user guide ›

Read the Low Latency Ethernet 10G MAC Agilex™ 5 FPGA IP Design Example user guide ›

Read the Low Latency Ethernet 10G MAC Stratix® 10 FPGA IP Design Example user guide ›

Read the Low Latency Ethernet 10G MAC Arria® 10 FPGA IP Design Example user guide ›

Read the Low Latency Ethernet 10G MAC Cyclone® 10 GX FPGA IP Design Example user guide ›

Read the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP user guide ›

Read the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example user guide ›

Low Latency Ethernet 10G MAC FPGA IP

The legacy 10G Ethernet MAC FPGA IP core continues to be offered with a full feature set for applications targeting Stratix® V FPGAs, and prior FPGA families.

The 10GE MAC and PHY function with various optional features is also available as hard IP on Stratix® 10 devices with E-tiles. More details can be found at Stratix® 10 FPGA E-Tile Hard IP for Ethernet IP Core.

Features

This FPGA IP core is designed to the IEEE 802.3–2008 Ethernet Standard, available on the IEEE website (www.ieee.org). All Low Latency 10GbE MAC FPGA IP core variations include only MAC in full-duplex mode. The core variations offer the following features:

MAC Features:

  • Full-duplex MAC in eight operating modes: 10G, 1G/10G, 1G/2.5G, 1G/2.5G/10G, 10M/100M/1G/2.5G/5G/10G (USXGMII), 10M/100M/1G/10G, 10M/100M/1G/2.5G, and 10M/100M/1G/2.5G/10G.
  • Three variations for selected operating modes: MAC TX block, MAC RX block, and MAC TX and RX blocks. A 10GBASE-R register mode on TX and RX datapaths enables lower latency.
  • Programmable promiscuous (transparent) mode.
  • Unidirectional feature specified by IEEE 802.3 (Clause 66). Priority-based flow control (PFC) with programmable pause quanta, supporting two to eight priority queues.
Interfaces:
  • Client-side: 32-bit Avalon® streaming interface (Avalon-ST).
  • Management: 32-bit Avalon-MM interface.
  • PHY-side: 32-bit XGMII for 10GbE, 16-bit GMII for 2.5GbE, 8-bit GMII for 1GbE, or 4-bit MII for 10M/100M.

Frame Structure Control Features:

  • Virtual local area network (VLAN) and stacked VLAN tagged frames decoding (type 'h8100).
  • Cyclic redundancy code (CRC)-32 computation and insertion on the TX datapath. Optional CRC checking and forwarding on the RX datapath.
  • Deficit idle counter (DIC) for optimized performance with average inter-packet gap (IPG) for LAN applications. Supports programmable IP.
  • Ethernet flow control using pause frames.
  • Programmable maximum length of transmit (TX) and receive (RX) data frames up to 64 kilobytes (KB).
  • Preamble passthrough mode on TX and RX datapaths, which allows user-defined preamble in the client frame.
  • Optional padding insertion on the TX datapath and termination on the RX datapath.

Frame Monitoring and Statistics:

  • Optional CRC checking and forwarding on the RX datapath.
  • Optional statistics collection on TX and RX datapaths.

Optional Timestamping, Specified in IEEE 1588v2, for the Following Configurations:

  • 10GbE MAC with 10GBASE-R PHY IP core.
  • 1G/10GbE MAC with 1G/10GbE PHY IP core.
  • 1G/2.5GbE MAC with 1G/2.5G Multirate Ethernet PHY IP core.
  • 1G/2.5G/10GbE MAC with 1G/2.5G/10G (MGBASE-T) Multirate Ethernet PHY IP core.
  • 10M/100M/1G/10GbE MAC with 10M-10GbE PHY IP core.
  • 10M/100M/1G/2.5G/5G/10G (USXGMII) MAC with 1G/2.5G/5G/10G Multirate Ethernet PHY FPGA IP core.

IP Status

 

Status

Production

Ordering Codes

Low Latency Ethernet 10G MAC FPGA IP (without the IEEE 1588v2 feature)

IP-10GEUMAC

Low Latency Ethernet 10G MAC FPGA IP(with the IEEE 1588v2 feature)

IP-10GEUMACF

10-Gbps Ethernet MAC MegaCore Function

IP-10GETHMAC

View all Show less

Related Links

Documentation

  • Low latency ethernet 10G MAC FPGA IP user guide
  • Legacy 10 Gbps ethernet MAC MegaCore function user guide
  • Low Latency Ethernet 10G MAC Agilex™ 5 FPGA IP user guide
  • Low Latency Ethernet 10G MAC Agilex™ 5 FPGA IP Design Example user guide
  • Low latency ethernet 10G MAC Stratix® 10 FPGA IP design example user guide
  • Low latency ethernet 10G MAC Arria® 10 FPGA IP design example user guide
  • Low latency ethernet 10G MAC Cyclone® 10 FPGA IP design example user guide

Development Boards

  • Stratix® 10 GX FPGA development kit
  • Stratix® 10 GX transceiver signal integrity development kit
  • Stratix® 10 TX signal integrity development kit
  • Arria® 10 GX transceiver signal integrity development kit
  • Arria® 10 GX FPGA development kit

Device Support

  • Agilex™ 5 FPGA
  • Stratix® 10 FPGA
  • Arria® 10 FPGA
  • Cyclone® 10 GX FPGA
  • Stratix® V FPGA
  • Arria® V FPGA
  • Cyclone® V FPGA
  • Stratix® IV FPGA
  • Arria® II FPGA
  • Cyclone® IV FPGA
  • FPGA IP release notes
  • FPGA IP for ethernet support center

Additional Resources

Find IP

Find the right Altera® FPGA Intellectual Property core for your needs.

Technical Support

For technical support on this IP core, please visit Support Resources or Intel® Premier Support. You may also search for related topics on this function in the Knowledge Center and Communities.

IP Evaluation and Purchase

Evaluation mode and purchasing information for Altera® FPGA Intellectual Property cores.

IP Base Suite

Free Altera® FPGA IP Core licenses with an active license for Quartus® Prime Standard or Pro Edition Software.

Design Examples

Download design examples and reference designs for Altera® FPGA devices.

Contact Sales

Get in touch with sales for your Altera® FPGA product design and acceleration needs.

Show more Show less
Compare Products
  • Company Overview
  • Contact Intel
  • Newsroom
  • Investors
  • Careers
  • Corporate Responsibility
  • Inclusion
  • Public Policy
  • © Intel Corporation
  • Terms of Use
  • *Trademarks
  • Cookies
  • Privacy
  • Supply Chain Transparency
  • Site Map
  • Recycling
  • Your Privacy Choices California Consumer Privacy Act (CCPA) Opt-Out Icon
  • Notice at Collection

Intel technologies may require enabled hardware, software or service activation. // No product or component can be absolutely secure. // Your costs and results may vary. // Performance varies by use, configuration, and other factors. Learn more at intel.com/performanceindex. // See our complete legal Notices and Disclaimers. // Intel is committed to respecting human rights and avoiding causing or contributing to adverse impacts on human rights. See Intel’s Global Human Rights Principles. Intel’s products and software are intended only to be used in applications that do not cause or contribute to adverse impacts on human rights.

Intel Footer Logo