This Intel® FPGA IP core is designed to the IEEE 802.3–2008 Ethernet Standard, available on the IEEE website (www.ieee.org). All Low Latency 10GbE MAC Intel® FPGA IP core variations include only MAC in full-duplex mode. The core variations offer the following features:
- Full-duplex MAC in eight operating modes: 10G, 1G/10G, 1G/2.5G, 1G/2.5G/10G, 10M/100M/1G/2.5G/5G/10G (USXGMII), 10M/100M/1G/10G, 10M/100M/1G/2.5G, and 10M/100M/1G/2.5G/10G.
- Three variations for selected operating modes: MAC TX block, MAC RX block, and MAC TX and RX blocks. A 10GBASE-R register mode on TX and RX datapaths enables lower latency.
- Programmable promiscuous (transparent) mode.
- Unidirectional feature specified by IEEE 802.3 (Clause 66). Priority-based flow control (PFC) with programmable pause quanta, supporting two to eight priority queues.
- Client-side: 32-bit Avalon® streaming interface (Avalon-ST).
- Management: 32-bit Avalon-MM interface.
- PHY-side: 32-bit XGMII for 10GbE, 16-bit GMII for 2.5GbE, 8-bit GMII for 1GbE, or 4-bit MII for 10M/100M.
Frame Structure Control Features:
- Virtual local area network (VLAN) and stacked VLAN tagged frames decoding (type 'h8100).
- Cyclic redundancy code (CRC)-32 computation and insertion on the TX datapath. Optional CRC checking and forwarding on the RX datapath.
- Deficit idle counter (DIC) for optimized performance with average inter-packet gap (IPG) for LAN applications. Supports programmable IP.
- Ethernet flow control using pause frames.
- Programmable maximum length of transmit (TX) and receive (RX) data frames up to 64 kilobytes (KB).
- Preamble passthrough mode on TX and RX datapaths, which allows user-defined preamble in the client frame.
- Optional padding insertion on the TX datapath and termination on the RX datapath.
Frame Monitoring and Statistics:
- Optional CRC checking and forwarding on the RX datapath.
- Optional statistics collection on TX and RX datapaths.
Optional Timestamping, Specified in IEEE 1588v2, for the Following Configurations:
- 10GbE MAC with 10GBASE-R PHY IP core.
- 1G/10GbE MAC with 1G/10GbE PHY IP core.
- 1G/2.5GbE MAC with 1G/2.5G Multirate Ethernet PHY IP core.
- 1G/2.5G/10GbE MAC with 1G/2.5G/10G (MGBASE-T) Multirate Ethernet PHY IP core.
- 10M/100M/1G/10GbE MAC with 10M-10GbE PHY IP core.
- 10M/100M/1G/2.5G/5G/10G (USXGMII) MAC with 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP core.