Low Latency Ethernet 10G MAC Intel® FPGA IP

The Low Latency Ethernet 10G MAC Intel FPGA IP core (soft IP) offers low round-trip latency, and an efficient resource footprint. The Intellectual Property (IP) core offers programmability of various features listed. This IP can be used in conjunction with the new Multi-Rate PHY Intel FPGA IP core to support the range of 10M/100M/1G to 10G data rates.

Read the low latency Ethernet 10G MAC Intel FPGA IP user guide ›

Read the 10-Gbps Ethernet MAC MegaCore function user guide ›

Read the low latency Ethernet 10G MAC Intel® Stratix® 10 FPGA IP design example user guide ›

Read the low latency Ethernet 10G MAC Intel® Arria® 10 FPGA IP design example user guide ›

Read the low latency Ethernet 10G MAC Intel® Cyclone® 10 GX FPGA IP design example user guide ›

Low Latency Ethernet 10G MAC Intel® FPGA IP

The legacy 10G Ethernet MAC Intel FPGA IP core continues to be offered with a full feature set for applications targeting Stratix® V FPGAs, and prior FPGA families.

The 10GE MAC and PHY function with various optional features is also available as hard IP on Intel Stratix 10 devices with E-tiles. More details can be found at Intel Stratix 10 FPGA E-Tile Hard IP for Ethernet IP Core.

Features

This Intel FPGA IP core is designed to the IEEE 802.3–2008 Ethernet Standard, available on the IEEE website (www.ieee.org). All Low Latency 10GbE MAC Intel FPGA IP core variations include only MAC in full-duplex mode. The core variations offer the following features:

MAC Features:

  • Full-duplex MAC in eight operating modes: 10G, 1G/10G, 1G/2.5G, 1G/2.5G/10G, 10M/100M/1G/2.5G/5G/10G (USXGMII), 10M/100M/1G/10G, 10M/100M/1G/2.5G, and 10M/100M/1G/2.5G/10G.
  • Three variations for selected operating modes: MAC TX block, MAC RX block, and MAC TX and RX blocks. A 10GBASE-R register mode on TX and RX datapaths enables lower latency.
  • Programmable promiscuous (transparent) mode.
  • Unidirectional feature specified by IEEE 802.3 (Clause 66). Priority-based flow control (PFC) with programmable pause quanta, supporting two to eight priority queues.
Interfaces:
  • Client-side: 32-bit Avalon® streaming interface (Avalon-ST) .
  • Management: 32-bit Avalon-MM interface.
  • PHY-side: 32-bit XGMII for 10GbE, 16-bit GMII for 2.5GbE, 8-bit GMII for 1GbE, or 4-bit MII for 10M/100M.

Frame Structure Control Features:

  • Virtual local area network (VLAN) and stacked VLAN tagged frames decoding (type 'h8100).
  • Cyclic redundancy code (CRC)-32 computation and insertion on the TX datapath. Optional CRC checking and forwarding on the RX datapath.
  • Deficit idle counter (DIC) for optimized performance with average inter-packet gap (IPG) for LAN applications. Supports programmable IP.
  • Ethernet flow control using pause frames.
  • Programmable maximum length of transmit (TX) and receive (RX) data frames up to 64 kilobytes (KB).
  • Preamble passthrough mode on TX and RX datapaths, which allows user-defined preamble in the client frame.
  • Optional padding insertion on the TX datapath and termination on the RX datapath.

Frame Monitoring and Statistics:

  • Optional CRC checking and forwarding on the RX datapath.
  • Optional statistics collection on TX and RX datapaths.

Optional Timestamping, Specified in IEEE 1588v2, for the Following Configurations:

  • 10GbE MAC with 10GBASE-R PHY IP core.
  • 1G/10GbE MAC with 1G/10GbE PHY IP core.
  • 1G/2.5GbE MAC with 1G/2.5G Multirate Ethernet PHY IP core.
  • 1G/2.5G/10GbE MAC with 1G/2.5G/10G (MGBASE-T) Multirate Ethernet PHY IP core.
  • 10M/100M/1G/10GbE MAC with 10M-10GbE PHY IP core.
  • 10M/100M/1G/2.5G/5G/10G (USXGMII) MAC with 1G/2.5G/5G/10G Multirate Ethernet PHY Intel FPGA IP core.

IP Quality Metrics

Basics

 

Low Latency

Year IP was first released

2012

2013

Latest version of Intel® Quartus® Prime design software supported

16.1

18.1

Status

Production

Production

Deliverables

 

Low Latency

Customer deliverables include the following:

    Design file (encrypted source code or post-synthesis netlist)

    Simulation model for ModelSim*- Intel FPGA Edition

    Timing and/or layout constraints

    Documentation with revision control

    Readme.txt file

Y

Y

Any additional customer deliverables provided with IP

 

 

Parameterization GUI allowing end user to configure IP

 

Y

 

Y

IP core is enabled for Intel FPGA IP Evaluation Mode Support

 

Y

 

Y

Source language

Verilog

Verilog

Testbench language

 

 

Software drivers provided

 N

N

Driver OS Support

 

 

Implementation

 

Low Latency

User interface

Avalon-ST (Datapath)

Avalon-MM (Management)

Avalon-ST (Datapath)

Avalon-MM (Management)

IP-XACT metadata

N

N

Verification

 

Low Latency

Simulators supported

Mentor Graphics*

Synopsys*

Cadence*

Mentor Graphics

Synopsys

Cadence

Hardware validated

Stratix® V

Intel Arria 10

Intel Stratix 10

Industry-standard compliance testing performed

UNH IEEE 802.3

UNH IEEE 802.3

If Yes, which tests?

Clause 4, 31, 46, and 49

Clause 4, 31, 46, and 49

If Yes, on which Intel FPGAs?

Stratix V

Stratix V

If Yes, date performed

2011

2015

If No, is it planned?

 

 

Interoperability

 

Low Latency

IP has undergone interoperability testing

Y

N

If yes, on which Intel FPGAs?

Stratix V

 

Interoperability reports available

Y