Low Latency Ethernet 10G MAC Intel® FPGA IP

The Low Latency Ethernet 10G MAC Intel® FPGA IP core (soft IP) offers low round-trip latency, and an efficient resource footprint. The Intellectual Property (IP) core offers programmability of various features listed. This IP can be used in conjunction with the new Multi-Rate PHY Intel® FPGA IP core to support the range of 10M/100M/1G to 10G data rates.

Read the Low Latency Ethernet 10G MAC Intel® FPGA IP user guide ›

Read the 10-Gbps Ethernet MAC MegaCore Function user guide ›

Read the Low Latency Ethernet 10G MAC Intel® Stratix® 10 FPGA IP Design Example user guide ›

Read the Low Latency Ethernet 10G MAC Intel® Arria® 10 FPGA IP Design Example user guide ›

Read the Low Latency Ethernet 10G MAC Intel® Cyclone® 10 GX FPGA IP Design Example user guide ›

Low Latency Ethernet 10G MAC Intel® FPGA IP

IP Quality Metrics

Basics

 

Low Latency

Year IP was first released

2012

2013

Latest version of Intel Quartus Prime Design Software supported

16.1

18.1

Status

Production

Production

Deliverables

 

Low Latency

Customer deliverables include the following:

    Design file (encrypted source code or post-synthesis netlist)

    Simulation model for ModelSim*- Intel FPGA Edition

    Timing and/or layout constraints

    Documentation with revision control

    Readme.txt file

Y

Y

Any additional customer deliverables provided with IP

 

 

Parameterization GUI allowing end user to configure IP

 

Y

 

Y

IP core is enabled for Intel FPGA IP Evaluation Mode Support

 

Y

 

Y

Source language

Verilog

Verilog

Testbench language

 

 

Software drivers provided

 N

N

Driver OS Support

 

 

Implementation

 

Low Latency

User interface

Avalon-ST (Datapath)

Avalon-MM (Management)

Avalon-ST (Datapath)

Avalon-MM (Management)

IP-XACT metadata

N

N

Verification

 

Low Latency

Simulators supported

Mentor Graphics*

Synopsys*

Cadence*

Mentor Graphics*

Synopsys*

Cadence*

Hardware validated

Stratix V

Intel Arria 10

Intel Stratix 10

Industry-standard compliance testing performed

UNH IEEE 802.3

UNH IEEE 802.3

If Yes, which tests?

Clause 4, 31, 46, and 49

Clause 4, 31, 46, and 49

If Yes, on which Intel FPGAs?

Stratix V

Stratix V

If Yes, date performed

2011

2015

If No, is it planned?

 

 

Interoperability

 

Low Latency

IP has undergone interoperability testing

Y

N

If yes, on which Intel FPGAs?

Stratix V

 

Interoperability reports available

Y