Low Latency Ethernet 10G MAC FPGA IP

The Low Latency Ethernet 10G MAC FPGA IP core (soft IP) offers low round-trip latency, and an efficient resource footprint. The Intellectual Property (IP) core offers programmability of various features listed. This IP can be used in conjunction with the new Multi-Rate PHY FPGA IP core to support the range of 10M/100M/1G to 10G data rates.

The low-latency 10G Ethernet MAC FPGA IP core continues to be offered with a full feature set for applications targeting Arria®  V, Arria®  10, Cyclone®  10 GX, Stratix® V FPGAs.

Features Agilex™ 7 and Agilex™ 9 (F-Tile) Agilex™ 3 and Agilex™ 5 Arria® V, Arria® 10, Cyclone® 10 GX, Stratix® V, Stratix® 10
MAC 
  • Full-duplex MAC in one operating mode: 10M/100M/1G/2.5G/5G/10G (USXGMII)
  • Variations for selected operating mode: Only both MAC TX and MAC RX block available
  • Programmable promiscuous (transparent) mode

 
  • Full-duplex MAC in eight operating modes: 10G, 1G/10G, 1G/2.5G, 1G/2.5G/10G, 10M/100M/1G/2.5G/5G/10G (USXGMII), 10M/100M/1G/10G, 10M/100M/1G/2.5G, and 10M/100M/1G/2.5G/10G
  • Three variations for selected operating modes: MAC TX only block, MAC RX only block, and both MAC TX and RX blocks
  • 10GBASE-R register mode on TX and RX datapaths enables lower latency
  • Programmable promiscuous (transparent) mode
  • Unidirectional feature specified by IEEE 802.3 (Clause 66)
  • Priority-based flow control (PFC) with programmable pause quanta, supporting two to eight priority queues
Interfaces
  • Client-side: 32-bit Avalon® streaming interface (Avalon-ST)
  • Management: 32-bit Avalon-MM interface
  • PHY-side: 32-bit XGMII for 10M/100M/1G/2.5G/5G/10G (USXGMII) operating mode
  • Client-side: 32-bit Avalon® streaming interface (Avalon-ST)
  • Management: 32-bit Avalon-MM interface
  • PHY-side: 32-bit XGMII for 10GbE, 16-bit GMII for 2.5GbE, 8-bit GMII for 1GbE, or 4-bit MII for 10M/100M
Frame Structure Control
  • Virtual local area network (VLAN) and stacked VLAN tagged frames decoding (type h8100, 88A8, 88F5, 9100, 9200)
  • Cyclic redundancy code (CRC)-32 computation and insertion on the TX datapath. Optional CRC checking and forwarding on the RX datapath
  • Deficit idle counter (DIC) for optimized performance with average inter-packet gap (IPG) for LAN applications
  • Supports programmable IPG
  • Ethernet flow control using pause frames
  • Programmable maximum length of TX and RX data frames up to 64 kilobytes (KB)
  • Optional padding insertion on the TX datapath and termination on the RX datapath
  • Virtual local area network (VLAN) and stacked VLAN tagged frames decoding (type h8100)
  • Cyclic redundancy code (CRC)-32 computation and insertion on the TX datapath. Optional CRC checking and forwarding on the RX datapath
  • Deficit Idle Counter (DIC) for optimized performance with average inter-packet gap (IPG) for LAN applications
  • Supports programmable IPG
  • Ethernet flow control using pause frames
  • Programmable maximum length of TX and receive RX data frames up to 64 kilobytes (KB)
  • Preamble passthrough mode on TX and RX datapaths, which allows user-defined preamble in the client frame
  • Optional padding insertion on the TX datapath and termination on the RX datapath.
Frame Monitoring Statistics

Optional CRC checking and forwarding on the RX datapath

Optional statistics collection on TX and RX datapaths
Optional Timestamping (specified in IEEE 1588v2)
  • 10M/100M/1G/2.5G/5G/10G (USXGMII) MAC with 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP core
  • 1G/2.5GbE MAC with 1G/2.5G Multirate Ethernet PHY IP core
  • 10M/100M/1G/2.5G/5G/10G (USXGMII) MAC with 10M/100M/1G/2.5G/5G/10G Multirate Ethernet PHY IP core
  • 10GbE MAC with 10GBASE-R PHY IP core.
  • 1G/10GbE MAC with 1G/10GbE PHY IP core.
  • 1G/2.5GbE MAC with 1G/2.5G Multirate Ethernet PHY IP core.
  • 1G/2.5G/10GbE MAC with 1G/2.5G/10G (MGBASE-T) Multirate Ethernet PHY IP core.
  • 10M/100M/1G/10GbE MAC with 10M-10GbE PHY IP core.
  • 10M/100M/1G/2.5G/5G/10G (USXGMII) MAC with 1G/2.5G/5G/10G Multirate Ethernet PHY FPGA IP core
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User Guides and Design Example User Guides

Agilex 3 and Agilex 5

FPGAs and SoCs

 Agilex 7 FPGA

(F-Tile) 

 Stratix 10 FPGA Arria 10 FPGA Cyclone 10 GX FPGA

User Guide

 User Guide

Design Example User Guide

Design Example User Guide

Design Example User Guide

Design Example User Guide

 Design Example User Guide
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Related Hard IP

The 10GE MAC and PHY function with various optional features is also available as a hard IP on Stratix® 10 and Agilex™ 7 devices with E-Tiles and on Agilex™ 7 and Agilex™ 9 devices with F-tiles.

For more details:  

IP Ordering Code Primary
Low Latency Ethernet 10G MAC FPGA IP (without the IEEE 1588v2 feature) IP-10GEUMAC

DigiKey

Mouser
Low Latency Ethernet 10G MAC FPGA IP (with the IEEE 1588v2 feature) IP-10GEUMACF

DigiKey

Mouser
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