Intel® FPGA Compute Express Link (CXL) IP
First FPGA shipping with CXL hard IP with up to 4x more bandwidth per port.1
Now with support for CXL specification revision 1.1 and 2.0.
Intel® FPGA Compute Express Link (CXL) IP
Available with Quartus Prime Design Software v22.3
Compute Express Link (CXL) is the new processor to peripheral/accelerator link protocol. It is based on and adds additional functionality beyond the existing PCIe protocol by allowing coherent communication between the two sides. This allows a CXL link to enable efficient, low-latency, high-bandwidth performance when used with Look-aside or Inline Accelerators for Heterogenous computing.
For those looking to create or use an FPGA-based accelerator, the CXL protocol Hard IP is available within the R-tile, which is incorporated in selected members of the Intel® Agilex™ I-series and Intel® Agilex™ M-series FPGA families. Hard IP allows for full bandwidth Gen5 x16 configuration support, with minimal use of FPGA fabric resources.
Implementing CXL Discrete Accelerators with Intel® Agilex™ FPGAs
Intel® Agilex™ FPGAs support CXL via R-Tile hard IP.
Available as hard IP2 (HIP) on R-Tile:
- Realize full Gen5 x16 performance
- Minimal fabric resources => more space for user logic
- Support for CXL spec. 1.1 and 2.0 (contact Intel for pricing and schedules).
FPGA support logic provided for each CXL device type:
- Accelerator Type 1 (Ordering Part Number: IP-CXLTYP1)
- Accelerator Type 2 (Ordering Part Number: IP-CXLTYP2)
- Memory expander Type 3 (Ordering Part Number: IP-CXLTYP3DDR)
- Includes FPGA design example, simulation model, and debug toolkit
Flexible device-attached memory subsystem architecture:
- Allows user to mix & manage different memory types/controllers
- M20K blocks, DDR4, DDR5, LPDDR5, HBM2e, SSD
IP Quality Metrics
Basics |
|
|---|---|
| Year IP was first released | 2022 |
| Status | Preliminary |
| Deliverables | |
Customer deliverables include the following: Design file (encrypted source code or post-synthesis netlist) Timing and/or layout constraints User Guide |
Y Y Y |
| Any additional customer deliverables provided with IP | Testbench, debug toolkit, and design examples |
To activate the CXL hard IP and receive CXL soft R-Tile Wrapper and Soft Support logic, purchase/activation of a separate CXL IP license is required for proper use with the Intel® Quartus® Prime Design Software. Contact your local Intel Sales representative for pricing details.
To activate a free-of-charge 30- or 60-day trial IP license, please contact your local Intel Sales representative.