Turbo Intel® FPGA IP

Forward-error correction (FEC) channel codes commonly improve the energy efficiency of wireless communication systems. Turbo codes are suitable for 3G and 4G mobile communications and satellite communications. You can use Turbo codes in other applications that require reliable information transfer over bandwidth- or latency-constrained communication links in the presence of data-corrupting noise. The 4G Turbo-V Intel® FPGA IP comprises a downlink and uplink accelerator for vRAN and includes the Turbo Intel® FPGA IP.

Turbo Intel® FPGA IP User Guide ›

Turbo-V Intel® FPGA IP User Guide ›

Turbo Intel® FPGA IP

Overview of the Turbo-V Intel® FPGA IP downlink and uplink accelerators.

Product Features

IP Functionality (downlink accelerator)

  • Code block cyclic redundancy code (CRC) attachment
  • Turbo encoder
  • Rate matcher with:
    • Subblock interleaver
    • Bit collector
    • Bit selector
    • Bit pruner
  • Adds redundancy to the data in the form of parity information

IP Functionality (uplink accelerator)

  • Subblock de-interleaver
  • Turbo decoder with CRC check
  • Exploits redundancy to correct a reasonable number of channel errors

Performance specifications

  • 3GPP LTE compliant with support for block sizes 40 to 6,144

User and system interfaces

  • Avalon®-Streaming (Avalon-ST) input and output interfaces

Debug and test capabilities

  • Provides C and MATLAB bit-accurate models for performance simulation and RTL test vector generation
  • Testbench and example design available

IP Status

Ordering Codes Status
Turbo : IP-TURBO Production
Turbo-V : IP-TURBOV Production
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Additional Resources

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