Turbo Intel® FPGA IP

The Turbo Intel FPGA IP core is a forward error correction code CODEC that supports the UMTS and LTE standards. The Turbo IP core can be parameterized as an encoder or decoder.

Read the Turbo Intel FPGA IP user guide ›

Turbo Intel® FPGA IP

Features

  • 3GPP LTE compliant
  • 3GPP UMTS compliant with support for block sizes from 40 to 5,114
  • C/MATLAB bit-accurate models for performance simulation or RTL test vector generation
Type Features

Decoder

  • Successive interface cancellation (SIC) for the LTE-A channel coding enhancement over LTE.
  • Runtime parameters for interleaver size and number of iterations.
  • Early termination with cyclical redundancy check (CRC).
  • Compile time parameters for the number of parallel engines, choice of decoding algorithm, input precision, and output size.
  • Double-buffering for reduced latency real-time applications, which allows the decoder to receive data while processing the previous data block.
  • No external memory required.

Encoder

  • 3GPP LTE and LTE-A compliant.
  • 3GPP UMTS compliant with support for block sizes from 40 to 5,114.
  • Runtime selectable interleaver block sizes.
  • Code rate 1/3 only.
  • Use external rate matching for other code rates.
  • Double-buffering allows the encoder to receive data while processing the previous data block.