FFT Intel® FPGA IP Core

The Fast Fourier transform (FFT) Intel FPGA intellectual property (IP) core is a high-performance, highly parameterizable FFT processor. The FFT function implements a radix-2/4 decimation-in-frequency (DIF) FFT algorithm for transform lengths of 2m where 6 ≤ m ≤ 14, internally using a block-floating-point architecture to maximize signal dynamic range in the transform calculation.

Read the FFT IP core user guide ›

FFT Intel® FPGA IP Core

What's New in v18.1:

The FFT Intel FPGA IP core accepts, as input, a complex data vector of length N (in two’s complement format) and outputs the transform-domain complex vector in natural order. An accumulated block exponent is output to indicate any data scaling that has occurred during the transform to maintain precision and maximize the internal signal-to-noise ratio. Transform direction is specifiable on a per-block basis via an input port.

Features

The FFT Intel FPGA IP core has the following options:

  • Radix-4 and mixed radix-2/4 implementations
  • Variable transform length
  • Block floating-point architecture—maximizes internal signal dynamic range
  • Use of internal memory

The FFT Intel FPGA IP core also:

  • Is optimized to use digital signal processing (DSP) blocks and TriMatrix memory architecture
  • Uses embedded multipliers
  • Has intellectual property (IP) functional simulation models for use in Intel FPGA supported VHDL and Verilog HDL simulators

Additional Resources

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Technical Support

For technical support on this IP core, please visit Support Resources or Intel® Premier Support. You may also search for related topics on this function in the Knowledge Center and Communities.

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