5G Polar Intel® FPGA IP

The 5G Polar Intel® FPGA IP implements a forward error correction (FEC) encoder and decoder based on polar codes compliant with the 3rd Generation Partnership Project (3GPP) 5G specification for integration into your wireless design. Polar codes represent an emerging class of error correction supporting the high throughput requirements for 5G new radio (NR).

5G Polar Intel® FPGA IP user guide ›

5G Polar Intel® FPGA IP

Overview of the 5G Polar Intel® FPGA IP Encoder and Decoder.

Product Features

IP Functionality

  • Encode and decode supported
  • Run-time configurable code block length, code rate, frozen bit and parity check bit locations, optional re-configured for each code block
  • Code block length can be 32, 64, 128, 256, 512 or 1024
  • Optional built-in bit allocation with uplink Polar decoder or downlink Polar encoder
  • Optional CRC, including CRC6, 11, 16, 24a, 24b and 24c
  • Optional DCI format with RNTI scrambling for CRC24c
  • Optional interleaving/de-interleaving
  • Successive Cancellation List decoding scheme, compile-time configurable list size, choosing from 4 or 8
  • Decoder output buffering allows the downstream to receive result while the decoder processes the next data block

Performance specifications

  • Complies with the 3GPP 5G Polar specification
  • Performance figures detailed in the User Guide

User and system interfaces

  • Avalon®-Streaming (Avalon-ST) input and output interfaces

Debug and test capabilities

  • Provides C and MATLAB bit-accurate models for performance simulation and RTL test vector generation
  • Testbench and example design available

IP Status

Ordering Code Status
IP-5G-POLAR Production
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