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  2. Altera® FPGA, SoC FPGA and CPLD
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  4. Digital Signal Processing IP Cores
  5. 5G LDPC Intel® FPGA IP

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5G LDPC Intel® FPGA IP

Low-density parity-check (LDPC) codes are linear error correcting codes that help you to transmit and receive messages over noisy channels. The 5G LDPC and LDPC-V Intel® FPGA IP implement LDPC codes compliant with the 3rd Generation Partnership Project (3GPP) 5G specification for integration in your wireless design. LDPC codes offer better spectral efficiency than Turbo codes and support the high throughput for 5G new radio (NR).

The 5G LDPC-V IP is a complete channel coding IP, optimized for virtual radio access networks (vRAN) and includes the 5G LDCP IP core.

5G LDPC Intel® FPGA IP user guide ›

5G LDPC-V Intel® FPGA IP user guide ›

5G LDPC Intel® FPGA IP

  • Overview

Overview of the 5G LDPC-V Intel® FPGA IP Encoder and Decoder.

Product Features

IP Functionality

  • Encode and decode supported
  • CRC checker module (CRC24B without concatenation)
  • Rate matcher
  • Per-block modifiable code block length and code rate
  • 5G LDPC-V Lite option for reduced resource usage
  • Improved block-error rate (BLER) performance for high reliability signal-to-noise ratios (SNRs) for ultra-reliable low-latency communications (URLLC)
  • Derate matcher
  • By passable hybrid automatic repeat request (HARQ) block
  • Code block segmentation CRC module (CRC24B without concatenation)
  • Per-block modifiable code block length, code rate, and maximum number of iterations
  • Configurable input precision
  • Layered decoder scheduling architecture to double the speed of convergence compared to non-layered architecture
  • Early termination based on the syndrome check using four layers or full syndrome after each iteration

Performance Specifications

  • Complies with the 3GPP 5G LDPC specification
  • No external memory requirement

User and System Interfaces

  • Avalon®-Streaming (Avalon-ST) input and output interfaces

Debug and Test Capabilities

  • Provides C and MATLAB bit-accurate models for performance simulation and RTL test vector generation
  • Testbench and example design available

IP Status

Ordering Code Status
LDPC : IP-5G-LDPC Production
LDPC-V : IP-LDPCV Production
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Related Links

Supported Devices

  • Agilex™ 5 FPGAs
  • Agilex™ 5 FPGAs D-Series
  • Agilex™ 5 FPGAs E-Series
  • Agilex™ 7 FPGAs
  • Stratix® 10 FPGAs
  • Arria® 10 FPGAs

Additional Resources

Find IP

Find the right Altera® FPGA Intellectual Property core for your needs.

Technical Support

For technical support on this IP core, please visit Support Resources or Intel® Premier Support. You may also search for related topics on this function in the Knowledge Center and Communities.

IP Evaluation and Purchase

Evaluation mode and purchasing information for Altera® FPGA Intellectual Property cores.

IP Base Suite

Free Altera® FPGA IP Core licenses with an active license for Quartus® Prime Standard or Pro Edition Software.

Design Examples

Download design examples and reference designs for Altera® FPGA devices.

Contact Sales

Get in touch with sales for your Altera® FPGA product design and acceleration needs.

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