Device Design Guidelines: Agilex™ 3 FPGAs and SoCs

ID 849807
Date 7/09/2025
Public
Document Table of Contents

4.3.2. HPS IP Instantiation in Quartus® Prime

You must instantiate the HPS IP using Platform Designer in Quartus® Prime.

For information about the HPS IP instantiation in Quartus® Prime, refer to Hard Processor System Component Reference Manual: Agilex™ 3 SoCs.

For information about the HPS IP and architecture, refer to Hard Processor System Technical Reference Manual Agilex™ 3 SoCs.