6.1. Synthesis Tool
                            
                        
                            
                            
                                6.2. Device Resource Reports
                            
                        
                            
                            
                                6.3. Quartus® Prime Message
                            
                        
                            
                            
                                6.4. Design Assistant Design Rule Checking
                            
                        
                            
                                6.5. Timing Constraints and Analysis
                            
                            
                        
                            
                            
                                6.6. Area and Timing Optimization
                            
                        
                            
                            
                                6.7. Preserving Performance and Reducing Compilation Time
                            
                        
                            
                            
                                6.8. Designing with Hyperflex®
                            
                        
                            
                            
                                6.9. Simulation
                            
                        
                            
                            
                                6.10. Power Analysis
                            
                        
                            
                            
                                6.11. Design Implementation, Analysis, Optimization and Verification Revision History
                            
                        
                    
                4.3.2. HPS IP Instantiation in Quartus® Prime
You must instantiate the HPS IP using Platform Designer in Quartus® Prime.
For information about the HPS IP instantiation in Quartus® Prime, refer to Hard Processor System Component Reference Manual: Agilex™ 3 SoCs.
For information about the HPS IP and architecture, refer to Hard Processor System Technical Reference Manual Agilex™ 3 SoCs.