2.1.1.1. Occasional equalization timeout or PCIe link training failure to achieve expected link speed during speed change, hot reset, and link disable
Description
Workaround
Status
2.1.1.2. Occasional receiver error recorded in the Advanced Error Reporting (AER) register during speed change and power management procedures
2.1.1.3. Both ERR_COR and ERR_FATAL messages are sent when TLP with ECRC error is received
2.1.1.4. Multiple error messages are generated by the multifunction device when a non-function-specific error occurs
2.1.1.5. Transmission of all Ethernet frames is suspended upon reception of PAUSE frame request from External link partner
2.1.1.6. Reduced Tx performance on GTS Ethernet FPGA Hard IP for 25GE line rate
2.1.2.1. The USB 3.1 controller has a spillover condition during IN transfers for bulk endpoint which causes a DBE issue for the ISOC-IN Endpoint
2.1.2.2. USB 3.1 Controller Device Drops eSS ISOC Data if the ITP Delta Value is Greater than 63 units
2.1.2.3. The USB 3.1 controller has a possible glitch on the clock output during U3 to U0 power state transition
2.1.1.1. Occasional equalization timeout or PCIe link training failure to achieve expected link speed during speed change, hot reset, and link disable
Description
In the GTS AXI Streaming IP for PCIe* , when you perform a speed change (at PCIe* 4.0 and PCIe* 3.0), hot reset, or link disable, in the worst case scenario, an equalization timeout or PCIe* link training failure could occur, preventing the link from achieving the expected speed.
Workaround
We recommend verifying the PCIe* link speed after a speed change, hot reset, or link disable procedure. If the PCIe* link speed does not meet expectations, repeat the speed change, hot reset, or link disable procedure to allow the link to recover at the desired speed.
Status
| Devices Affected | Planned Fix |
|---|---|
|
None |