1. About This Document 2. Known Issue List for Agilex™ 5 Devices 3. Document Revision History for the Agilex™ 5 Known Issue List

2.1. FPGA

2.1.1. Transceiver 2.1.2. HPS

2.1.1.1. Occasional equalization timeout or PCIe link training failure to achieve expected link speed during speed change, hot reset, and link disable Description Workaround Status 2.1.1.2. Occasional receiver error recorded in the Advanced Error Reporting (AER) register during speed change and power management procedures 2.1.1.3. Both ERR_COR and ERR_FATAL messages are sent when TLP with ECRC error is received 2.1.1.4. Multiple error messages are generated by the multifunction device when a non-function-specific error occurs 2.1.1.5. Transmission of all Ethernet frames is suspended upon reception of PAUSE frame request from External link partner 2.1.1.6. Reduced Tx performance on GTS Ethernet FPGA Hard IP for 25GE line rate 2.1.1.7. GTS HDMI IP and GTS PMA/FEC Direct PHY IP with HDMI configuration rule are not of production quality 2.1.1.8. GTS SDI II FPGA IP and GTS PMA/FEC Direct PHY FPGA IP with SDI configuration rule are not of production quality 2.1.1.9. DisplayPort IP Performance Instability Issue 2.1.1.10. Reduced Reference Clock Frequency Options for Certain Output Frequencies in GTS System PLL Clocks IP 2.1.1.11. IEEE 1588v2 PTP Accuracy Issue for GTS Ethernet Hard IP for 10GE Rate Designs 2.1.1.12. IEEE 1588v2 PTP Accuracy Issue for GTS Ethernet Hard IP for 25GE Rate Designs in Dynamically Reconfigurable Mode 2.1.1.13. Deterministic Latency Accuracy Issue for Inter-protocol Designs in Dynamic Reconfiguration Controller IP

2.1.2.1. The USB 3.1 controller has a spillover condition during IN transfers for bulk endpoint which causes a DBE issue for the ISOC-IN Endpoint 2.1.2.2. USB 3.1 Controller Device Drops eSS ISOC Data if the ITP Delta Value is Greater than 63 units 2.1.2.3. The USB 3.1 controller has a possible glitch on the clock output during U3 to U0 power state transition 2.1.2.4. HPS GICv3 ITS unable to access physical memory larger than 32 bits causing MSI-X Interrupt failure 2.1.2.5. SD/eMMC Host Controller Capabilities Register provides incorrect information with regard to 8-bit Embedded Device Support