2.1.1.1. Occasional equalization timeout or PCIe link training failure to achieve expected link speed during speed change, hot reset, and link disable
2.1.1.2. Occasional receiver error recorded in the Advanced Error Reporting (AER) register during speed change and power management procedures
2.1.1.3. Both ERR_COR and ERR_FATAL messages are sent when TLP with ECRC error is received
2.1.1.4. Multiple error messages are generated by the multifunction device when a non-function-specific error occurs
2.1.1.5. Transmission of all Ethernet frames is suspended upon reception of PAUSE frame request from External link partner
2.1.1.6. Reduced Tx performance on GTS Ethernet FPGA Hard IP for 25GE line rate
2.1.2.1. The USB 3.1 controller has a spillover condition during IN transfers for bulk endpoint which causes a DBE issue for the ISOC-IN Endpoint
2.1.2.2. USB 3.1 Controller Device Drops eSS ISOC Data if the ITP Delta Value is Greater than 63 units
2.1.2.3. The USB 3.1 controller has a possible glitch on the clock output during U3 to U0 power state transition
1. About This Document
This document provides information about known issues affecting the Agilex™ 5 production devices.
Currently, this document covers the following Ordering Part Numbers (OPNs) of the Agilex™ 5 production devices:
| Agilex™ 5 Orderable Part Numbers (OPNs) |
|---|
A5Ex013xxxxxxxx A5Ex008xxxxxxxx A5Ex013xxxxxxxxCS A5Ex008xxxxxxxxCS |
Figure 1. Agilex™ 5 FPGAs and SoCs Ordering Part NumberUse this OPN Decoder to determine your device variant.
This document includes Altera-specific known issues for the Agilex™ 5 production devices.
For known issues affecting the Agilex™ 5 ES devices, refer to the Agilex™ 5 ES Device Errata and User Guidelines.
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