Embedded Memory User Guide: Agilex™ 3 FPGAs and SoCs

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ID 849316
Date 5/22/2025
Public
Document Table of Contents
Document Table of Contents x
1. Agilex™ 3 Embedded Memory Overview 2. Agilex™ 3 Embedded Memory Architecture and Features 3. Agilex™ 3 Embedded Memory Design Considerations 4. Agilex™ 3 Embedded Memory IP References 5. Agilex™ 3 Embedded Memory Debugging 6. Document Revision History for the Embedded Memory User Guide: Agilex™ 3 FPGAs and SoCs
1. Agilex™ 3 Embedded Memory Overview x
1.1. Agilex™ 3 Embedded Memory Features 1.2. Agilex™ 3 Embedded Memory Block Signals
2. Agilex™ 3 Embedded Memory Architecture and Features x
2.1. Byte Enable in Agilex™ 3 Embedded Memory Blocks 2.2. Address Hold Support 2.3. Asynchronous Clear and Synchronous Clear 2.4. Memory Blocks Error Correction Code Support 2.5. Agilex™ 3 Embedded Memory Clocking Modes 2.6. Agilex™ 3 Embedded Memory Configurations 2.7. Force-to-Zero 2.8. Coherent Read Memory 2.9. Freeze Logic 2.10. True Dual Port Dual Clock Emulator 2.11. Initial Value of Read and Write Address Registers 2.12. Automatic Timing/Power Optimization in M20K Blocks
2.1. Byte Enable in Agilex™ 3 Embedded Memory Blocks x
2.1.1. Byte Enable Controls 2.1.2. Data Byte Output 2.1.3. Byte Enable Behavior
2.4. Memory Blocks Error Correction Code Support x
2.4.1. Error Correction Code Truth Table 2.4.2. Parity Bit 2.4.3. ECC Parity Flip 2.4.4. ECC Read-During-Write Behavior
2.5. Agilex™ 3 Embedded Memory Clocking Modes x
2.5.1. Single Clock Mode 2.5.2. Read/Write Clock Mode 2.5.3. Input/Output Clock Mode 2.5.4. Asynchronous/Synchronous Clears in Clocking Modes 2.5.5. Output Read Data in Simultaneous Read/Write 2.5.6. Independent Clock Enables in Clocking Modes
2.6. Agilex™ 3 Embedded Memory Configurations x
2.6.1. Mixed-Width Port Configurations
2.8. Coherent Read Memory x
2.8.1. Forwarding Logic
2.10. True Dual Port Dual Clock Emulator x
2.10.1. True Dual-Port Mixed Port Read During Write New Data Emulation
3. Agilex™ 3 Embedded Memory Design Considerations x
3.1. Consider the Memory Block Selection 3.2. Consider the Concurrent Write Behavior 3.3. Read-During-Write 3.4. Consider Power-Up State and Memory Initialization 3.5. Reduce Power Consumption 3.6. Avoid Providing Non-Deterministic Input 3.7. Avoid Changing Clock Signals and Other Control Signals Simultaneously 3.8. Advanced Settings in Quartus® Prime Software for Memory 3.9. Consider the Memory Depth Setting 3.10. Consider Registering the Memory Output
3.3. Read-During-Write x
3.3.1. Customize Read-During-Write Behavior
3.3.1. Customize Read-During-Write Behavior x
3.3.1.1. Same-Port Read-During-Write Mode 3.3.1.2. Mixed-Port Read-During-Write Mode 3.3.1.3. Read-During-Write Data Output and Memory Location Behaviors
4. Agilex™ 3 Embedded Memory IP References x
4.1. On-Chip Memory RAM and ROM IPs 4.2. FIFO Intel® FPGA IP 4.3. Shift Register (RAM-based) IP
4.1. On-Chip Memory RAM and ROM IPs x
4.1.1. Release Information for RAM and ROM IPs 4.1.2. Features 4.1.3. Implementation Guide 4.1.4. Parameters and Interface Signals
4.1.2. Features x
4.1.2.1. On-Chip Memory RAM and ROM IPs
4.1.3. Implementation Guide x
4.1.3.1. Instantiating IP Cores using the Quartus® Prime Parameter Editor 4.1.3.2. Changing Parameter Settings Manually
4.1.4. Parameters and Interface Signals x
4.1.4.1. RAM: 1-PORT FPGA IP Parameters 4.1.4.2. RAM: 2-PORT FPGA IP Parameters 4.1.4.3. RAM: 4-PORT FPGA IP Parameters 4.1.4.4. ROM: 1-PORT FPGA IP Parameters 4.1.4.5. ROM: 2-PORT FPGA IP Parameters 4.1.4.6. RAM and ROM Manual Parameter Settings 4.1.4.7. RAM and ROM Interface Signals
4.2. FIFO Intel® FPGA IP x
4.2.1. Release Information for FIFO Intel® FPGA IP 4.2.2. Features 4.2.3. Implementation Guide 4.2.4. Parameters and Interface Signals 4.2.5. Design Considerations
4.2.3. Implementation Guide x
4.2.3.1. Instantiating IP Cores using Quartus® Prime Pro Edition Parameter Editor 4.2.3.2. Manual IP Instantiation through HDL
4.2.3.2. Manual IP Instantiation through HDL x
4.2.3.2.1. Verilog HDL Prototype 4.2.3.2.2. VHDL Component Declaration 4.2.3.2.3. VHDL LIBRARY-USE Declaration 4.2.3.2.4. HDL Code from Parameterizable Macros Template 4.2.3.2.5. Coding Example for Manual Instantiation 4.2.3.2.6. Instantiation Template
4.2.4. Parameters and Interface Signals x
4.2.4.1. FIFO Signals 4.2.4.2. FIFO Parameter Settings 4.2.4.3. FIFO Intel® FPGA IP Parameters
4.2.5. Design Considerations x
4.2.5.1. FIFO Functional Timing Requirements 4.2.5.2. SCFIFO ALMOST_EMPTY Functional Timing 4.2.5.3. FIFO Output Status Flag and Latency 4.2.5.4. FIFO Metastability Protection and Related Options 4.2.5.5. FIFO Synchronous Clear and Asynchronous Clear Effect 4.2.5.6. SCFIFO and DCFIFO Show-Ahead Mode 4.2.5.7. Different Input and Output Width 4.2.5.8. DCFIFO Timing Constraint Setting 4.2.5.9. Gray-Code Counter Transfer at the Clock Domain Crossing 4.2.5.10. Guidelines for Embedded Memory ECC Feature 4.2.5.11. Reset Scheme
4.2.5.5. FIFO Synchronous Clear and Asynchronous Clear Effect x
4.2.5.5.1. Recovery and Removal Timing Violation Warnings when Compiling a DCFIFO
4.2.5.8. DCFIFO Timing Constraint Setting x
4.2.5.8.1. Embedded Timing Constraint 4.2.5.8.2. User Configurable Timing Constraint
4.2.5.8.2. User Configurable Timing Constraint x
4.2.5.8.2.1. SDC Commands
4.3. Shift Register (RAM-based) IP x
4.3.1. Release Information for Shift Register (RAM-based) IP 4.3.2. Features 4.3.3. Implementation Guide 4.3.4. Parameters and Interface Signals
4.3.3. Implementation Guide x
4.3.3.1. Instantiating IP Cores using Quartus® Prime Pro Edition Parameter Editor
4.3.4. Parameters and Interface Signals x
4.3.4.1. Shift Register (RAM-based) IP Parameter Settings 4.3.4.2. Shift Register Ports and Parameters Setting
1. Agilex™ 3 Embedded Memory Overview
2. Agilex™ 3 Embedded Memory Architecture and Features
3. Agilex™ 3 Embedded Memory Design Considerations
4. Agilex™ 3 Embedded Memory IP References
5. Agilex™ 3 Embedded Memory Debugging
6. Document Revision History for the Embedded Memory User Guide: Agilex™ 3 FPGAs and SoCs

4.2.5.11. Reset Scheme

During power-up, the registers are in undefined power and reset states. To guarantee correct functionality, reset the FIFO IP upon completion of configuration by asserting either the sclr or aclr signal.

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