Embedded Memory User Guide: Agilex™ 3 FPGAs and SoCs

ID 849316
Date 5/22/2025
Public
Document Table of Contents

4.3.2. Features

The Shift Register (RAM-based) IP implements a shift register with taps and offers additional features, which include:
  • Selectable RAM block type
  • A wide range of widths for the shiftin and shiftout ports
  • Support for output taps at certain points in the shift register chain
  • Selectable distance between taps