Embedded Memory User Guide: Agilex™ 3 FPGAs and SoCs

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ID 849316
Date 5/22/2025
Public
Document Table of Contents
Document Table of Contents x
1. Agilex™ 3 Embedded Memory Overview 2. Agilex™ 3 Embedded Memory Architecture and Features 3. Agilex™ 3 Embedded Memory Design Considerations 4. Agilex™ 3 Embedded Memory IP References 5. Agilex™ 3 Embedded Memory Debugging 6. Document Revision History for the Embedded Memory User Guide: Agilex™ 3 FPGAs and SoCs
1. Agilex™ 3 Embedded Memory Overview x
1.1. Agilex™ 3 Embedded Memory Features 1.2. Agilex™ 3 Embedded Memory Block Signals
2. Agilex™ 3 Embedded Memory Architecture and Features x
2.1. Byte Enable in Agilex™ 3 Embedded Memory Blocks 2.2. Address Hold Support 2.3. Asynchronous Clear and Synchronous Clear 2.4. Memory Blocks Error Correction Code Support 2.5. Agilex™ 3 Embedded Memory Clocking Modes 2.6. Agilex™ 3 Embedded Memory Configurations 2.7. Force-to-Zero 2.8. Coherent Read Memory 2.9. Freeze Logic 2.10. True Dual Port Dual Clock Emulator 2.11. Initial Value of Read and Write Address Registers 2.12. Automatic Timing/Power Optimization in M20K Blocks
2.1. Byte Enable in Agilex™ 3 Embedded Memory Blocks x
2.1.1. Byte Enable Controls 2.1.2. Data Byte Output 2.1.3. Byte Enable Behavior
2.4. Memory Blocks Error Correction Code Support x
2.4.1. Error Correction Code Truth Table 2.4.2. Parity Bit 2.4.3. ECC Parity Flip 2.4.4. ECC Read-During-Write Behavior
2.5. Agilex™ 3 Embedded Memory Clocking Modes x
2.5.1. Single Clock Mode 2.5.2. Read/Write Clock Mode 2.5.3. Input/Output Clock Mode 2.5.4. Asynchronous/Synchronous Clears in Clocking Modes 2.5.5. Output Read Data in Simultaneous Read/Write 2.5.6. Independent Clock Enables in Clocking Modes
2.6. Agilex™ 3 Embedded Memory Configurations x
2.6.1. Mixed-Width Port Configurations
2.8. Coherent Read Memory x
2.8.1. Forwarding Logic
2.10. True Dual Port Dual Clock Emulator x
2.10.1. True Dual-Port Mixed Port Read During Write New Data Emulation
3. Agilex™ 3 Embedded Memory Design Considerations x
3.1. Consider the Memory Block Selection 3.2. Consider the Concurrent Write Behavior 3.3. Read-During-Write 3.4. Consider Power-Up State and Memory Initialization 3.5. Reduce Power Consumption 3.6. Avoid Providing Non-Deterministic Input 3.7. Avoid Changing Clock Signals and Other Control Signals Simultaneously 3.8. Advanced Settings in Quartus® Prime Software for Memory 3.9. Consider the Memory Depth Setting 3.10. Consider Registering the Memory Output
3.3. Read-During-Write x
3.3.1. Customize Read-During-Write Behavior
3.3.1. Customize Read-During-Write Behavior x
3.3.1.1. Same-Port Read-During-Write Mode 3.3.1.2. Mixed-Port Read-During-Write Mode 3.3.1.3. Read-During-Write Data Output and Memory Location Behaviors
4. Agilex™ 3 Embedded Memory IP References x
4.1. On-Chip Memory RAM and ROM IPs 4.2. FIFO Intel® FPGA IP 4.3. Shift Register (RAM-based) IP
4.1. On-Chip Memory RAM and ROM IPs x
4.1.1. Release Information for RAM and ROM IPs 4.1.2. Features 4.1.3. Implementation Guide 4.1.4. Parameters and Interface Signals
4.1.2. Features x
4.1.2.1. On-Chip Memory RAM and ROM IPs
4.1.3. Implementation Guide x
4.1.3.1. Instantiating IP Cores using the Quartus® Prime Parameter Editor 4.1.3.2. Changing Parameter Settings Manually
4.1.4. Parameters and Interface Signals x
4.1.4.1. RAM: 1-PORT FPGA IP Parameters 4.1.4.2. RAM: 2-PORT FPGA IP Parameters 4.1.4.3. RAM: 4-PORT FPGA IP Parameters 4.1.4.4. ROM: 1-PORT FPGA IP Parameters 4.1.4.5. ROM: 2-PORT FPGA IP Parameters 4.1.4.6. RAM and ROM Manual Parameter Settings 4.1.4.7. RAM and ROM Interface Signals
4.2. FIFO Intel® FPGA IP x
4.2.1. Release Information for FIFO Intel® FPGA IP 4.2.2. Features 4.2.3. Implementation Guide 4.2.4. Parameters and Interface Signals 4.2.5. Design Considerations
4.2.3. Implementation Guide x
4.2.3.1. Instantiating IP Cores using Quartus® Prime Pro Edition Parameter Editor 4.2.3.2. Manual IP Instantiation through HDL
4.2.3.2. Manual IP Instantiation through HDL x
4.2.3.2.1. Verilog HDL Prototype 4.2.3.2.2. VHDL Component Declaration 4.2.3.2.3. VHDL LIBRARY-USE Declaration 4.2.3.2.4. HDL Code from Parameterizable Macros Template 4.2.3.2.5. Coding Example for Manual Instantiation 4.2.3.2.6. Instantiation Template
4.2.4. Parameters and Interface Signals x
4.2.4.1. FIFO Signals 4.2.4.2. FIFO Parameter Settings 4.2.4.3. FIFO Intel® FPGA IP Parameters
4.2.5. Design Considerations x
4.2.5.1. FIFO Functional Timing Requirements 4.2.5.2. SCFIFO ALMOST_EMPTY Functional Timing 4.2.5.3. FIFO Output Status Flag and Latency 4.2.5.4. FIFO Metastability Protection and Related Options 4.2.5.5. FIFO Synchronous Clear and Asynchronous Clear Effect 4.2.5.6. SCFIFO and DCFIFO Show-Ahead Mode 4.2.5.7. Different Input and Output Width 4.2.5.8. DCFIFO Timing Constraint Setting 4.2.5.9. Gray-Code Counter Transfer at the Clock Domain Crossing 4.2.5.10. Guidelines for Embedded Memory ECC Feature 4.2.5.11. Reset Scheme
4.2.5.5. FIFO Synchronous Clear and Asynchronous Clear Effect x
4.2.5.5.1. Recovery and Removal Timing Violation Warnings when Compiling a DCFIFO
4.2.5.8. DCFIFO Timing Constraint Setting x
4.2.5.8.1. Embedded Timing Constraint 4.2.5.8.2. User Configurable Timing Constraint
4.2.5.8.2. User Configurable Timing Constraint x
4.2.5.8.2.1. SDC Commands
4.3. Shift Register (RAM-based) IP x
4.3.1. Release Information for Shift Register (RAM-based) IP 4.3.2. Features 4.3.3. Implementation Guide 4.3.4. Parameters and Interface Signals
4.3.3. Implementation Guide x
4.3.3.1. Instantiating IP Cores using Quartus® Prime Pro Edition Parameter Editor
4.3.4. Parameters and Interface Signals x
4.3.4.1. Shift Register (RAM-based) IP Parameter Settings 4.3.4.2. Shift Register Ports and Parameters Setting
1. Agilex™ 3 Embedded Memory Overview
2. Agilex™ 3 Embedded Memory Architecture and Features
3. Agilex™ 3 Embedded Memory Design Considerations
4. Agilex™ 3 Embedded Memory IP References
5. Agilex™ 3 Embedded Memory Debugging
6. Document Revision History for the Embedded Memory User Guide: Agilex™ 3 FPGAs and SoCs

4.1.4.6. RAM and ROM Manual Parameter Settings

Table 60.   Parameters for altera_syncram Use this parameter list if you manually edit the design file.
Name Legal Values Description
operation_mode
  • SINGLE_PORT
  • DUAL_PORT
  • BIDIR_DUAL_PORT
  • QUAD_PORT
  • ROM

Operation mode of the memory block.
width_a —

Data width of port A.
widthad_a —

Address width of port A.
numwords_a —

Number of data words in the memory block for port A.
outdata_reg_a
  • UNREGISTERED
  • CLOCK1
  • CLOCK0

Clock for the data output registers of port A.
outdata_aclr_a
  • NONE
  • CLEAR1
  • CLEAR0

Asynchronous clear for data output registers of port A.

If you set the outdata_reg_a parameter to UNREGISTERED, outdata_aclr_a specifies the clearing parameter for the output latch.

address_aclr_a
  • NONE
  • CLEAR0

Option to clear the address input registers of port A.
width_byteena_a —

Width of the byte-enable bus of port A.

The width must be equal to the value of width_a divided by the byte size. The default value of 1 is allowed only if you do not use byte-enable.

width_b —

Data width of port B.
widthad_b —

Address width of port B.
numwords_b —

Number of data words in the memory block for port B.
outdata_reg_b
  • UNREGISTERED
  • CLOCK1
  • CLOCK0

Clock for the data output registers of port B.
address_reg_b
  • CLOCK1
  • CLOCK0

Clock for the address registers of port B.
outdata_aclr_b
  • NONE
  • CLEAR1
  • CLEAR0

Asynchronous clear for data output registers of port B.

If you set the outdata_reg_b parameter to UNREGISTERED, outdata_aclr_b specifies the clearing parameter for the output latch.

address_aclr_b
  • NONE
  • CLEAR0

Option to clear the address input registers of port B.
width_byteena_b —

Width of the byte-enable bus of port B.

The width must be equal to the value of width_b divided by the byte size. The default value of 1 is allowed only if you do not use byte-enable.

intended_device_family "Agilex"

Parameter used for simulation purpose.
ram_block_type
  • AUTO
  • M20K
  • MLAB

The memory block type.
byte_size
  • 5
  • 8
  • 9
  • 10

The byte size for the byte-enable mode.
read_during_write_ mode_mixed_ports
  • DONT_CARE
  • CONSTRAINT_DONT_CARE
  • NEW_DATA
  • OLD_DATA
  • NEW_A_OLD_B

Specify the behavior for read-during-write mode.

  • The default value is DONT_CARE.
  • The value of NEW_DATA is supported only if:
    • The read address and output data are registered by the write clock in the LUTRAM mode; or
    • You select true dual port mode for M20K.
  • The value of CONSTRAINED_DONT_CARE is supported only in LUTRAM mode.
  • The value of NEW_A_OLD_B is supported only if you set the operation_mode parameter to QUAD_PORT.
init_file
  • *.mif
  • *.hex
The initialization file.
init_file_layout
  • PORT_A
  • PORT_B
The layout of the initialization file.
maximum_depth — The depth of the memory block slices.
clock_enable_input_a
  • NORMAL
  • BYPASS
The clock enable for the input registers of port A.
clock_enable_output_a
  • NORMAL
  • BYPASS
The clock enable for the output registers of port A.
clock_enable_input_b
  • NORMAL
  • BYPASS
The clock enable for the input registers of port B.
clock_enable_output_b
  • NORMAL
  • BYPASS
The clock enable for the output registers of port B.
read_during_write_ mode_port_a
  • NEW_DATA_NO_NBE_READ
  • NEW_DATA_WITH_NBE_READ
  • OLD_DATA
  • DONT_CARE
The read-during-write behavior for port A.
read_during_write_ mode_port_b
  • NEW_DATA_NO_NBE_READ
  • NEW_DATA_WITH_NBE_READ
  • OLD_DATA
  • DONT_CARE
The read-during-write behavior for port B.
enable_ecc
  • TRUE
  • FALSE
Turns ECC on or off.
ecc_pipeline_stage_ enabled
  • TRUE
  • FALSE

Turns ECC pipeline registers before the output decoder on or off.

Turning on this feature allows ECC mode to achieve the same performance as the non-ECC mode but at the cost of one cycle of latency.

  • The default value is FALSE.
  • If you set this parameter to TRUE:
    • You must set enable_ecc to TRUE.
    • You cannot set outdata_reg_b parameter to UNREGISTERED.
enable_ecc_encoder_bypass
  • TRUE
  • FALSE

Turns ECC encoder bypass on or off.

If you set this parameter to TRUE, you must set enable_ecc to TRUE.

enable_coherent_read
  • TRUE
  • FALSE

Turns coherent read on or off.

The default value is FALSE.

enable_force_to_zero
  • TRUE
  • FALSE

Turns Force-to-Zero on or off.

The default value is FALSE.

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