Pin Connection Guidelines: Agilex™ 3 FPGAs and SoCs

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ID 846812
Date 8/13/2025
Public
Document Table of Contents
Document Table of Contents x
1. Pin Connection Guidelines: Agilex™ 3 FPGAs and SoCs
1. Pin Connection Guidelines: Agilex™ 3 FPGAs and SoCs x
1.1. Pin Connection Guideline Status for Agilex™ 3 Devices 1.2. Agilex™ 3 FPGA Core Pins 1.3. Agilex™ 3 GTS Transceiver Pins 1.4. Agilex™ 3 Hard Processor System (HPS) Pins 1.5. Power Supply Sharing Guidelines for Agilex™ 3 Devices 1.6. Notes to Agilex™ 3 Pin Connection Guidelines 1.7. Document Revision History for the Pin Connection Guidelines: Agilex™ 3 FPGAs and SoCs
1.2. Agilex™ 3 FPGA Core Pins x
1.2.1. Clock and PLL Pins 1.2.2. Dedicated Configuration/JTAG Pins 1.2.3. Optional/Dual-Purpose Configuration Pins 1.2.4. Differential I/O Pins 1.2.5. External Memory Interface Pins 1.2.6. Voltage Sensor and Voltage Reference Pins 1.2.7. Remote Temperature Sensing Diode Pins 1.2.8. Reference Pins 1.2.9. HVIO GPIO Pins 1.2.10. HVIO Optional Function Pins 1.2.11. No Connect and DNU Pins 1.2.12. Power Supply Pins 1.2.13. Secure Device Manager (SDM) Pins 1.2.14. Secure Device Manager (SDM) Optional Signal Pins
1.3. Agilex™ 3 GTS Transceiver Pins x
1.3.1. GTS Transceiver Power Supply Pins 1.3.2. GTS Transceiver Pins
1.4. Agilex™ 3 Hard Processor System (HPS) Pins x
1.4.1. HPS Power Supply Pins 1.4.2. HPS Oscillator Clock Input Pin 1.4.3. HPS JTAG Pins 1.4.4. HPS GPIO Pins 1.4.5. HPS SDMMC Pins 1.4.6. HPS NAND Pins 1.4.7. HPS USB Pins 1.4.8. HPS EMAC Pins 1.4.9. HPS I2C_EMAC and MDIO Pins 1.4.10. HPS I2C Pins 1.4.11. HPS I3C Pins 1.4.12. HPS SPI Pins 1.4.13. HPS UART Pins 1.4.14. HPS Trace Pins
1.5. Power Supply Sharing Guidelines for Agilex™ 3 Devices x
1.5.1. Example 1— Agilex™ 3 Devices with Speed Grade -6S and -7S
1. Pin Connection Guidelines: Agilex™ 3 FPGAs and SoCs

1.1. Pin Connection Guideline Status for Agilex™ 3 Devices

Note: The pin connection guideline statuses in this document represent the full Agilex™ 3 device family, which includes packages still in development. For the data sheet status of a specific Agilex™ 3 device, refer to the Agilex™ 3 FPGAs and SoCs Device Data Sheet. For the Agilex™ 3 device pin-out status, refer to the device pin-out file.

The following descriptors designate the status level currently applicable to the relevant variant:

  • Preliminary: Information in this document is subject to change. Intended for pre-production development, for production designs use with caution.
  • Final: Information in this document is intended for use in production design.
Table 1.  Pin Connection Guideline Status for Agilex™ 3 Devices
Tile Status
Core Pins Preliminary
HPS Pins Preliminary
GTS Transceiver Pins Preliminary
HVIO Pins Preliminary
Level Two Title