Pin Connection Guidelines: Agilex™ 3 FPGAs and SoCs

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ID 846812
Date 8/13/2025
Public
Document Table of Contents
Document Table of Contents x
1. Pin Connection Guidelines: Agilex™ 3 FPGAs and SoCs
1. Pin Connection Guidelines: Agilex™ 3 FPGAs and SoCs x
1.1. Pin Connection Guideline Status for Agilex™ 3 Devices 1.2. Agilex™ 3 FPGA Core Pins 1.3. Agilex™ 3 GTS Transceiver Pins 1.4. Agilex™ 3 Hard Processor System (HPS) Pins 1.5. Power Supply Sharing Guidelines for Agilex™ 3 Devices 1.6. Notes to Agilex™ 3 Pin Connection Guidelines 1.7. Document Revision History for the Pin Connection Guidelines: Agilex™ 3 FPGAs and SoCs
1.2. Agilex™ 3 FPGA Core Pins x
1.2.1. Clock and PLL Pins 1.2.2. Dedicated Configuration/JTAG Pins 1.2.3. Optional/Dual-Purpose Configuration Pins 1.2.4. Differential I/O Pins 1.2.5. External Memory Interface Pins 1.2.6. Voltage Sensor and Voltage Reference Pins 1.2.7. Remote Temperature Sensing Diode Pins 1.2.8. Reference Pins 1.2.9. HVIO GPIO Pins 1.2.10. HVIO Optional Function Pins 1.2.11. No Connect and DNU Pins 1.2.12. Power Supply Pins 1.2.13. Secure Device Manager (SDM) Pins 1.2.14. Secure Device Manager (SDM) Optional Signal Pins
1.3. Agilex™ 3 GTS Transceiver Pins x
1.3.1. GTS Transceiver Power Supply Pins 1.3.2. GTS Transceiver Pins
1.4. Agilex™ 3 Hard Processor System (HPS) Pins x
1.4.1. HPS Power Supply Pins 1.4.2. HPS Oscillator Clock Input Pin 1.4.3. HPS JTAG Pins 1.4.4. HPS GPIO Pins 1.4.5. HPS SDMMC Pins 1.4.6. HPS NAND Pins 1.4.7. HPS USB Pins 1.4.8. HPS EMAC Pins 1.4.9. HPS I2C_EMAC and MDIO Pins 1.4.10. HPS I2C Pins 1.4.11. HPS I3C Pins 1.4.12. HPS SPI Pins 1.4.13. HPS UART Pins 1.4.14. HPS Trace Pins
1.5. Power Supply Sharing Guidelines for Agilex™ 3 Devices x
1.5.1. Example 1— Agilex™ 3 Devices with Speed Grade -6S and -7S
1. Pin Connection Guidelines: Agilex™ 3 FPGAs and SoCs

1.3.1. GTS Transceiver Power Supply Pins

Note: Altera recommends that you create a Quartus® Prime design, enter your device I/O assignments, and compile the design. The Quartus® Prime software checks your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device user guides.
Table 16.  GTS Transceiver Power Supply Pins
Pin Name Pin Functions Pin Description Connection Guidelines

VCC_HSSI_L1

 Power

GTS transceiver digital logic power supply.

  • For the devices with speed grade –6S, it is 0.78-V.
  • For the devices with speed grade –7S, it is 0.75- V.

For more information about the supported pins, refer to the device pin-out file.

Connect VCC_HSSI to low noise switching regulator. Refer to the Power Distribution Network Design Guidelines section in the PCB Layout, Routing, and Power Distribution Network Design Guidelines: Agilex™ 3 FPGAs and SoCs for the decoupling capacitor requirement.

Do not tie it to GND or leave it floating if unused.
VCCEHT_GTSL1A Power

GTS transceiver high-voltage analog power supply pins.

For more information about the supported pins, refer to the device pin-out file.

VCCEHT_GTS should share 1.8-V rail with VCCPT through a proper isolation filtering. Refer to PCB Layout, Routing, and Power Distribution Network Design Guidelines: Agilex™ 3 FPGAs and SoCs for fitter details and decoupling capacitor requirement.

Tie to GND for power down only if you do not plan to use it in the future. Refer to the Unused PMA Not Planned for Use in the Future section in the GTS Transceiver PHY User Guide: Agilex™ 3 FPGAs and SoCs for more details about the GTS transceiver banks that support power down.
VCCERT_GTSL1A Power

GTS transceiver analog 1.0-V logic power pins.

For more information about the supported pins, refer to the device pin-out file.

Connect VCCERT_GTS to 1.0-V dedicated regulator. Refer to PCB Layout, Routing, and Power Distribution Network Design Guidelines: Agilex™ 3 FPGAs and SoCs for decoupling capacitor requirement.

Tie to GND for power down only if you do not plan to use it in the future. Refer to the Unused PMA Not Planned for Use in the Future section in the GTS Transceiver PHY User Guide: Agilex™ 3 FPGAs and SoCs for more details about the GTS transceiver banks that support power down.
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