Pin Connection Guidelines: Agilex™ 3 FPGAs and SoCs

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ID 846812
Date 6/11/2025
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Document Table of Contents
Document Table of Contents x
1. Pin Connection Guidelines: Agilex™ 3 FPGAs and SoCs
1. Pin Connection Guidelines: Agilex™ 3 FPGAs and SoCs x
1.1. Pins Status for Agilex™ 3 Devices 1.2. Agilex™ 3 FPGA Core Pins 1.3. Agilex™ 3 GTS Transceiver Pins 1.4. Agilex™ 3 Hard Processor System (HPS) Pins 1.5. Power Supply Sharing Guidelines for Agilex™ 3 Devices 1.6. Notes to Agilex™ 3 Pin Connection Guidelines 1.7. Document Revision History for the Pin Connection Guidelines: Agilex™ 3 FPGAs and SoCs
1.2. Agilex™ 3 FPGA Core Pins x
1.2.1. Clock and PLL Pins 1.2.2. Dedicated Configuration/JTAG Pins 1.2.3. Optional/Dual-Purpose Configuration Pins 1.2.4. Differential I/O Pins 1.2.5. External Memory Interface Pins 1.2.6. Voltage Sensor and Voltage Reference Pins 1.2.7. Remote Temperature Sensing Diode Pins 1.2.8. Reference Pins 1.2.9. HVIO GPIO Pins 1.2.10. HVIO Optional Function Pins 1.2.11. No Connect and DNU Pins 1.2.12. Power Supply Pins 1.2.13. Secure Device Manager (SDM) Pins 1.2.14. Secure Device Manager (SDM) Optional Signal Pins
1.3. Agilex™ 3 GTS Transceiver Pins x
1.3.1. GTS Transceiver Power Supply Pins 1.3.2. GTS Transceiver Pins
1.4. Agilex™ 3 Hard Processor System (HPS) Pins x
1.4.1. HPS Power Supply Pins 1.4.2. HPS Oscillator Clock Input Pin 1.4.3. HPS JTAG Pins 1.4.4. HPS GPIO Pins 1.4.5. HPS SDMMC Pins 1.4.6. HPS NAND Pins 1.4.7. HPS USB Pins 1.4.8. HPS EMAC Pins 1.4.9. HPS I2C_EMAC and MDIO Pins 1.4.10. HPS I2C Pins 1.4.11. HPS I3C Pins 1.4.12. HPS SPI Pins 1.4.13. HPS UART Pins 1.4.14. HPS Trace Pins
1.5. Power Supply Sharing Guidelines for Agilex™ 3 Devices x
1.5.1. Example 1— Agilex™ 3 Devices with Speed Grade -6S and -7S
1. Pin Connection Guidelines: Agilex™ 3 FPGAs and SoCs

1.2.5. External Memory Interface Pins

Note: Altera recommends that you create a Quartus® Prime design, enter your device I/O assignments, and compile the design. The Quartus® Prime software checks your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device user guides.
Table 6.  External Memory Interface Pins
Pin Name Pin Functions Pin Description Connection Guidelines
DQS[0:63] I/O, bidirectional

Optional data strobe signal for use in external memory interfacing. These pins drive to the dedicated DQS phase shift circuitry.

Supported I/O standards:

  • LVSTL 1.1-V I/O standard

Connect unused pins as defined in the Quartus® Prime software.

If the entire HSIO bank is unused, you may leave these pins floating, connected to VCCIO_PIO, or connected to a tri-stated upstream or downstream I/O pin. If the unused pins reside in an active HSIO bank, you may leave these pins floating or connected to a tri-stated upstream or downstream I/O pin.

DQSn[0:63] I/O, bidirectional

Optional complementary data strobe signal for use in external memory interfacing. These pins drive to the dedicated DQS phase shift circuitry.

Supported I/O standards:

  • LVSTL 1.1-V I/O standard

Connect unused pins as defined in the Quartus® Prime software.

If the entire HSIO bank is unused, you may leave these pins floating, connected to VCCIO_PIO, or connected to a tri-stated upstream or downstream I/O pin. If the unused pins reside in an active HSIO bank, you may leave these pins floating or connected to a tri-stated upstream or downstream I/O pin.

DQ[0:63] I/O, bidirectional

Optional data signal for use in external memory interfacing. Analyze the available DQ pins across all pertinent DQS columns in the device pin-out file.

Supported I/O standards:

  • LVSTL 1.1-V I/O standard

For the DQ pin swapping guidelines, refer to the External Memory Interfaces (EMIF) IP User Guide: Agilex™ 3 FPGA and SoCs .

Connect unused pins as defined in the Quartus® Prime software.

If the entire HSIO bank is unused, you may leave these pins floating, connected to VCCIO_PIO, or connected to a tri-stated upstream or downstream I/O pin. If the unused pins reside in an active HSIO bank, you may leave these pins floating or connected to a tri-stated upstream or downstream I/O pin.

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