Logic Array Blocks and Adaptive Logic Modules User Guide: Agilex™ 3 FPGAs and SoCs

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ID 846637
Date 4/07/2025
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2.1.1. MLAB

Each MLAB supports a maximum of 640 bits of simple dual-port SRAM. You can configure each ALM in an MLAB as a 32 (depth) x 2 (width) memory block, resulting in a configuration of 32 (depth) x 20 (width) simple dual-port SRAM block.

Figure 2.  Agilex™ 3 LAB and MLAB Structure
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